Top-Gate TFT Patterning for Stable Channel Length in OLED Displays
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Solution Overview
Problem
The manufacturing process of OLED display substrates often results in suboptimal morphology of the gate insulation layer, leading to a short channel region under the gate insulation layer, which deteriorates the threshold voltage characteristic of TFTs and affects the product quality of display devices.
Innovation Solution
A manufacturing method for a top-gate type thin film transistor on a display substrate involves forming a photoresist film layer with a specific thickness and slope angle, using it as a protection mask for over-etching the gate and gate insulation layers, and performing a conductive treatment to the active layer, ensuring a good morphology of the gate insulation layer and maintaining the channel region's length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching method is used for gate insulation layer, then etching process is simple, but gate insulation layer morphology is poor and channel region becomes short
Solution Approach 1:
The photoresist film is formed with a predetermined thickness of 1.8-2.2 μm and slope angle of not less than 70° before etching, creating optimal conditions in advance for the subsequent etching process. This preliminary preparation ensures that the gate insulation layer will be etched to the correct depth without requiring complex real-time control during etching.
Solution Approach 2:
The patent specifies precise parameters for the photoresist film including thickness (1.8-2.2 μm) and slope angle (not less than 70°). By controlling these parameters, the etching process achieves proper gate insulation layer morphology and maintains adequate channel region length without requiring complex process adjustments.
2Reliability
If photoresist film thickness is increased to prevent etching residue, then etching residue is prevented, but photoresist material consumption increases
Solution Approach 1:
The patent optimizes the photoresist film thickness to a specific range of 1.8-2.2 μm, which is sufficient to prevent etching residue and maintain reliable TFT operation while minimizing photoresist material consumption. This precise parameter control balances reliability with material efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method improves the threshold voltage characteristic of TFTs and enhances the product quality of display devices by preventing etching residue and ensuring a proper gate insulation layer morphology, thus maintaining the channel region's integrity.
Implementation Method 1
exposing the photoresist film layer to a light using a mask as a protection mask
Implementation Method 2
over-etching the gate insulation film layer by a gaseous corrosion method to form a gate insulation layer
Data Source
AI summary
A manufacturing method of a display substrate, a display substrate, and a display device. The manufacturing method includes: forming an active layer; forming a gate insulation film layer, a gate film layer and a photoresist film layer; exposing the photoresist film layer to a light and developing the exposed photoresist film layer until the developed photoresist film layer has a thickness of 1.8-2.2 μm and a slope angle not less than 70°; over-etching the gate film layer to form a gate electrode, an orthographic projection of the gate electrode being located within a region of an orthographic projection of the developed photoresist film layer; over-etching the gate insulation film layer by a gaseous corrosion method to form a gate insulation layer; peeling off the photoresist film layer remaining on a surface of the gate electrode; and performing a conductive treatment to the active layer.