Top Gate TFT Semiconductor Patterning for OLED Manufacturing
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Solution Overview
Problem
The manufacturing process for OLED display devices using top gate type thin film transistors is complex and requires numerous expensive process steps, necessitating a reduction in processing steps to improve efficiency and cost-effectiveness.
Innovation Solution
A method for forming a thin film transistor with a reduced number of processing steps, involving a substrate with a gate electrode, gate insulating layer, semiconductor layer, source and drain electrodes, and a planarization layer, where the semiconductor layer is patterned to include doped and non-doped areas, and a conductive layer and pixel electrode are formed to minimize contact resistance, using a half-tone mask for patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional manufacturing processes for top gate type thin film transistors are used, then device performance is achieved, but the number of processing steps is large and manufacturing complexity increases
Solution Approach 1:
The patent combines the formation of source and drain electrodes with the patterning of the semiconductor layer into a single simultaneous patterning step. This merging of operations reduces the total number of processing steps while maintaining the required device structure and electrical performance of the top gate thin film transistor
2Manufacturing precision
If multiple masks are used for patterning, then precise alignment is achieved, but manufacturing cost and process complexity increase
Solution Approach 1:
The invention employs a single mask to simultaneously pattern both the semiconductor layer and the source/drain electrodes. This approach maintains precise alignment through one controlled masking step while eliminating the need for multiple sequential masks, thereby reducing process complexity and manufacturing cost
3Reliability
If conventional patterning methods are used, then device structure is formed, but contact resistance between electrodes and semiconductor layer increases
Solution Approach 1:
The patent forms the semiconductor layer and source/drain electrodes in simultaneous contact during the patterning step, ensuring proper alignment and contact before subsequent processing. This preliminary establishment of contact geometry prevents misalignment issues that would increase contact resistance, while the single-step process maintains manufacturing efficiency
Data Source
AI summary
A thin film transistor (TFT) may include a substrate, a gate electrode on the substrate, a gate insulating layer on the gate electrode, and a semiconductor layer on the gate insulating layer. The semiconductor layer may include a top surface, a channel area aligned in a vertical direction with the gate electrode, a plurality of doped areas proximate to the channel area, and a plurality of non-doped areas. Source and drain electrodes may be on the top surface of the semiconductor layer aligned above respective ones of the plurality of non-doped areas of the semiconductor layer. A planarization layer may be on the gate insulating layer, the source and drain electrodes and the semiconductor layer channel area, and may include a plurality of openings respectively exposing the plurality of doped areas of the semiconductor layer and a portion of the source electrode and the drain electrode.