Top Metal Spacing and Fill Layout for ILD Crack Mitigation
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Solution Overview
Problem
Multilevel metallization structures in semiconductor dies face performance degradation and potential device failure due to interfacial delamination and ILD cracking caused by poor fracture strength and brittle mechanical behavior of interlevel or interlayer dielectric (ILD) layers.
Innovation Solution
The implementation of a metallization structure with top metal features that extend in orthogonal directions, with controlled spacing and lateral overlap of conductive terminals, mitigates ILD cracking by reducing stress levels and crack risks through finite element modeling and selective filling of top metal structures to compensate for high metal density gradients.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If top metal structures are placed close together to reduce device area, then area utilization is improved, but ILD stress and crack risk increase
Solution Approach 1:
The patent applies local quality by creating non-uniform metal density distribution through selective filling of top metal structures. Areas with high stress concentration receive different metal density treatment compared to low stress areas, optimizing both area utilization and crack mitigation locally where needed
Solution Approach 2:
The patent changes the metal density parameter selectively in different regions of the top metal layer. By adjusting the filling ratio of top metal structures based on local stress conditions, the patent optimizes the balance between area utilization and ILD crack prevention
2Reliability
If top metal structures are spaced far apart to reduce ILD stress, then ILD crack risk is reduced, but device area increases
Solution Approach 1:
The patent applies local quality by differentiating metal structure spacing based on local stress conditions. High stress regions receive larger spacing to reduce crack risk, while low stress regions maintain smaller spacing for better area utilization
Solution Approach 2:
The patent applies partial action by selectively spacing out only those top metal structures that contribute to high stress concentration, rather than uniformly spacing all structures. This partial application of spacing achieves crack mitigation without excessive area consumption
3Area of stationary object
If metal density gradients are high to maximize area utilization, then area efficiency is improved, but ILD stress concentration increases
Solution Approach 1:
The patent applies local quality by creating spatially varying metal density that matches the local stress distribution. Areas with low stress concentration can have high metal density for area efficiency, while high stress areas have reduced density to minimize stress concentration
Solution Approach 2:
The patent changes the metal density parameter as a function of location, creating controlled density gradients that follow the stress distribution pattern. This parameter optimization balances area utilization with stress management
Data Source
AI summary
An electronic device includes a semiconductor die having a semiconductor body, a metallization structure over the semiconductor body and a conductive terminal, the metallization structure including a top level having neighboring first and second top metal structures that extend in a plane of orthogonal first and second directions, the first top metal structure is electrically coupled to the conductive terminal, the conductive terminal extends over a portion of the first top metal structure and away from the plane along a third direction orthogonal to the first and second directions, and the first top metal structure is spaced apart from the second top metal structure in the plane by a spacing distance of 60 μm or more.