Top Metal Sidewall Profile for Crack-Resistant Passivation Coverage
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Solution Overview
Problem
In semiconductor manufacturing, the increasing density of functional devices leads to resistive-capacitive delay issues due to poor covering conditions and cracks in the protection layer of the metal interconnect structure, affecting product yield and reliability.
Innovation Solution
A top metal structure with two sidewalls of different slopes is used to improve the covering condition of the passivation layer, reducing the likelihood of cracks and enhancing manufacturing yield and reliability by conformally forming the passivation layer on the interlayer dielectric and top metal structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the top metal is made much thicker than the protection layer to reduce resistance, then the resistance of the metal interconnect structure is reduced, but the covering condition of the protection layer deteriorates and cracks are generated
Solution Approach 1:
The top metal structure is divided into two distinct portions: a bottom portion with a first sidewall and a top portion with a second sidewall. This segmentation allows each portion to have optimized sidewall slopes, where the bottom portion provides structural support and the top portion ensures proper protection layer coverage, thereby resolving the contradiction between thickness requirements and covering conditions.
Solution Approach 2:
Different portions of the top metal structure are given different local geometric properties. The bottom portion has a steeper sidewall slope while the top portion has a gentler sidewall slope. This local differentiation allows the structure to simultaneously achieve low resistance (through sufficient thickness) and good protection layer coverage (through optimized local geometry at the top portion).
2Reliability
If the top metal is made much thicker than the protection layer to reduce resistance, then the resistance of the metal interconnect structure is reduced, but cracks are generated in the protection layer
Solution Approach 1:
By segmenting the top metal into bottom and top portions with different sidewall slopes, the structure creates a more favorable geometry for protection layer formation. The gentler second sidewall at the top portion reduces stress concentration points, preventing crack generation while maintaining the necessary metal thickness for low resistance.
Solution Approach 2:
The sidewall slope parameter is changed differently for the bottom and top portions of the metal structure. The bottom portion maintains a steeper slope for structural integrity, while the top portion uses a gentler slope to reduce stress on the protection layer, thereby preventing cracks while preserving the low-resistance benefit of increased metal thickness.
3Reliability
If a protection layer is formed to cover the top metal and ILD, then the metal interconnect structure is protected, but poor covering condition and cracks occur because the top metal is much thicker than the protection layer
Solution Approach 1:
The top metal structure is segmented into bottom and top portions with different sidewall characteristics. This segmentation creates a geometry that naturally facilitates better protection layer coverage without requiring additional complex structural elements or processes, thus improving reliability while maintaining relatively simple device complexity.
Data Source
AI summary
A connection structure of a semiconductor device is provided in the present invention. The connection structure includes an interlayer dielectric, a top metal structure, and a passivation layer. The interlayer dielectric is disposed on a substrate. The top metal structure is disposed on the interlayer dielectric. The top metal structure includes a bottom portion and a top portion disposed on the bottom portion. The bottom portion includes a first sidewall, and the top portion includes a second sidewall. A slope of the first sidewall is larger than a slope of the second sidewall. The passivation layer is conformally disposed on the second sidewall, the first sidewall, and a top surface of the interlayer dielectric.