Top Plate Boosting Circuit for Sampling Switch Linearity

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Solution Overview

Problem

As CMOS fabrication processes advance to smaller geometries and lower power supply voltages, it becomes challenging to maintain a low 'on' resistance for the top plate sampling switch in switched capacitor circuits, leading to linearity issues and increased noise, especially at high frequencies, due to the limitations of existing bootstrapping techniques.

Innovation Solution

A top plate boosting circuit that generates a boosted gate voltage for the top plate sampling switch by combining the common mode voltage with a fixed DC voltage, allowing the gate voltage to track process, temperature, and supply voltage variations, thereby optimizing the 'on' resistance without increasing switch size or using local charge pumps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If power supply voltage is decreased to achieve lower power dissipation, then power consumption is reduced, but the effective gate to source voltage of sampling transistors decreases leading to higher 'on' resistance and linearity issues

Engineering Contradiction:

Improvepower dissipationVSAvoidlinearity and on-resistance

Core Design Contradiction:

Loss of energyVSReliability

Solution Approach 1:

The patent changes the voltage parameter by introducing a boosted gate voltage (VG) that is higher than the power supply voltage (VDD). This is achieved by coupling the gate of the sampling transistor to a voltage source that provides VDD plus an additional voltage increment, thereby maintaining low 'on' resistance and good linearity even when VDD is reduced for lower power consumption.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If switch size is increased to reduce 'on' resistance, then on-resistance decreases, but device area increases leading to higher manufacturing cost and power consumption

Engineering Contradiction:

Improveon-resistanceVSAvoidswitch area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

Instead of increasing the physical size of the sampling switch, the patent changes the electrical parameter by applying a boosted gate voltage. This voltage enhancement allows the same-sized transistor to achieve lower 'on' resistance and better linearity, avoiding the need for larger device area.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If conventional bootstrapping techniques are used for top plate sampling switch, then gate voltage is boosted, but linearity issues and noise increase at high frequencies due to voltage variations

Engineering Contradiction:

Improvegate voltage boostingVSAvoidnoise and linearity degradation

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent replaces the conventional bootstrapping mechanism with a direct voltage boosting approach. Instead of using a bootstrapped capacitor network that is susceptible to high-frequency variations and noise, the invention directly couples the gate to a stable boosted voltage source, eliminating the harmful effects of bootstrapping at high frequencies.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution maintains low 'on' resistance and linearity for the top plate sampling switch across varying conditions, reducing noise and power consumption, while ensuring transistor reliability and efficient sampling network performance.

Implementation Method 1

Methodology Applied

Scientific EffectVoltage combination and tracking:

Data Source

PatentUS7816951B1Locally boosted top plate sampling for a sampling capacitor

Publication Date: 2010.10.19 NAT SEMICON CORP

AI summary

An analog sampling network (100) includes a sampling capacitor being coupled between a bottom plate sampling switch and a top plate sampling switch implemented as NMOS transistors. The top plate sampling switch has source/drain terminals coupled respectively to the sampling capacitor and a first reference voltage. The analog sampling network includes a top plate boosting circuit (150) providing a boosted gate voltage to a gate terminal of the top plate sampling switch during a sampling phase, the boosted gate voltage being the sum of a first voltage and a second voltage. The first voltage is approximately equal to the first reference voltage and tracks process, temperature, power supply voltage and biasing condition variations. The second voltage is a maximum operating voltage from the gate to drain/source terminal for a fabrication process used to fabricate the second MOS transistor.