Top Select Gate Trench Segmentation for Crack-Free 3D NAND
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Solution Overview
Problem
In 3D NAND flash memory devices, the high aspect ratio and depth of top select gate (TSG) trenches pose challenges for etching and filling, often resulting in deformed etching profiles and crack defects during thermal processes, especially when using a single photomask for trench printing.
Innovation Solution
The method involves printing the TSG trench using two photomasks, forming separate dielectric trenches in the core and staircase regions, which allows for individual control of trench depths and avoids the need for holes that complicate etching and filling, thereby reducing the risk of crack formation during thermal processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If TSG trench is printed on a single photomask, then the trench depth can be controlled, but the etching profile becomes deformed and crack defects form during thermal process
Solution Approach 1:
The patent divides the TSG trench formation into two separate photomask steps: first forming the main trench structure, then forming additional trenches to achieve the final depth. This segmentation allows each etching step to work on a shallower profile, preventing deformation and crack formation while still achieving the required total depth precision.
2Ease of manufacture
If holes are added to TSG trenches to facilitate filling, then the filling process becomes easier, but the etching profile is deformed and crack defects are formed
Solution Approach 1:
Instead of adding holes to a single deep trench, the patent segments the trench into multiple shallower trenches formed by different photomasks. This allows the filling process to proceed without requiring holes, as each individual trench is shallow enough to be filled properly while maintaining profile integrity and avoiding crack defects.
3Productivity
If trench depth is increased to achieve higher density, then memory capacity increases, but etching and filling become increasingly difficult
Solution Approach 1:
The patent achieves increased memory density through multiple photomask steps that create overlapping trench patterns. Each individual etching step operates on a manageable depth scale, while the cumulative effect of multiple trenches achieves the required total depth for high-density storage, thereby maintaining ease of manufacture while increasing productivity.
Solution Approach 2:
The patent transitions from a single-dimension approach (one deep trench per location) to a multi-dimensional approach (multiple overlapping trenches from different photomasks). This dimensional change allows the system to achieve greater effective depth through spatial multiplication rather than single deep etching, reducing the difficulty of each individual etching and filling operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the etching and filling process, reduces the complexity of TSG trench formation, and prevents crack defects, enabling more precise control over trench depths and improving the reliability of the semiconductor device.
Implementation Method 1
printing the TSG trench using two photomasks
Implementation Method 2
forming separate dielectric trenches in the core and staircase regions
Implementation Method 3
forming separate dielectric trenches in the core and staircase regions
Data Source
AI summary
Aspects of the disclosure provide a method for fabricating a semiconductor device having an first stack of alternating insulating layers and sacrificial word line layers arranged over a substrate, the first stack including a core region and a staircase region. The method can include forming a first dielectric trench in the core region of the first stack, forming a second dielectric trench that is adjacent to and connected with the first dielectric trench in the staircase region of the first stack, and forming dummy channel structures extending through the first stack where the dummy channel structures are spaced apart from the second dielectric trench.