Top-Side Pin Array Packaging for Smaller, More Reliable Stacks
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Solution Overview
Problem
Existing semiconductor packages and manufacturing methods are inadequate, leading to excess cost, decreased reliability, and oversized packages.
Innovation Solution
A method for manufacturing an electronic device with a top side pin array, involving a substrate with pads, forming solder members on the pads, using a pin template with apertures aligned with the pads, and attaching pins to the pads before reflowing the solder.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor packaging methods are used, then manufacturing process is established, but cost is excessive and reliability is decreased
Solution Approach 1:
The patent applies preliminary action by forming solder members on the substrate pads before attaching the pins. This sequence ensures proper alignment and bonding, improving reliability while maintaining manufacturing efficiency. The solder members are prepared in advance, allowing for controlled reflow processing that enhances joint strength without requiring expensive post-assembly repairs.
2Area of stationary object
If conventional semiconductor packaging methods are used, then manufacturing process is established, but package size becomes too large
Solution Approach 1:
The patent implements dimensionality change by transitioning from traditional lateral pin arrangements to a vertical stacking configuration with pins extending from the top surface of the substrate. This three-dimensional arrangement significantly reduces the lateral footprint of the package while maintaining all necessary electrical connections, thereby decreasing package size without compromising manufacturability.
3Productivity
If pins are attached before solder reflow, then manufacturing efficiency is improved, but alignment precision must be maintained
Solution Approach 1:
The patent uses the solder members as an intermediary element between the substrate pads and the pins. The pins are attached to the solder members, which are already positioned on the pads. This intermediary layer facilitates alignment and bonding, allowing for efficient manufacturing processes while maintaining the necessary precision through the self-aligning nature of the solder reflow process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces costs, increases reliability, and enhances manufacturability by enabling efficient pin attachment and solder reflow, potentially facilitating three-dimensional stacking.
Implementation Method 1
attaching pins to the pads before reflowing the solder
Data Source
AI summary
An electronic device and a manufacturing method thereof. As non-limiting examples, various aspects of this disclosure provide an electronic device having a top side pin array, for example which may be utilized for three-dimensional stacking, and a method for manufacturing such an electronic device.