Top-Side Power Delivery With Vapor Chamber for Lower Package Losses
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Solution Overview
Problem
Conventional computing systems experience significant power losses and increased package size due to the traditional power delivery path from the voltage regulator to the processing unit die, which limits performance and thermal design point (TDP) efficiency.
Innovation Solution
A 3D power architecture is integrated into thermal solutions, delivering power from the top side of the semiconductor package, reducing overall power losses by 50-80% and partitioning power and IO vertically, thereby enhancing performance and maintaining small form factors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power is delivered through the motherboard and package substrate from the voltage regulator to the die, then the processing unit can receive operating voltage, but power losses increase squared to the current (I²R losses)
Solution Approach 1:
The patent transitions from a conventional planar power delivery path (through motherboard and package substrate) to a three-dimensional architecture where power is delivered from the top side of the semiconductor package. This dimensional change shortens the current path and reduces resistance, thereby decreasing I²R power losses while maintaining performance.
Solution Approach 2:
Instead of delivering power from the bottom side through the package substrate as in conventional designs, the patent inverts the approach by delivering power from the top side of the semiconductor package. This reversal of the power delivery direction significantly reduces the path length and resistance, lowering power losses.
2Productivity
If the TDP increases to meet performance requirements, then processing performance improves, but power losses increase squared to the current
Solution Approach 1:
By implementing top-side power delivery in a three-dimensional semiconductor package architecture, the patent reduces the power delivery path length and resistance. This allows the system to achieve higher TDP and performance levels without proportionally increasing power losses, as the I²R losses are mitigated by the shortened current path.
3Loss of energy
If power and IO are partitioned vertically in a 3D architecture, then power losses are reduced by 50-80% and performance is enhanced, but the device complexity increases
Solution Approach 1:
The patent implements vertical partitioning of power and IO functions in a three-dimensional semiconductor package, separating them into different layers or regions. This spatial separation reduces interference between power and signal paths, shortens current loops, and decreases power losses while managing complexity through structured layering.
Solution Approach 2:
The patent segments the semiconductor package into distinct functional regions, separating power delivery pathways from IO signal pathways. This segmentation allows independent optimization of each function, reducing electromagnetic interference and power losses while maintaining manageable device complexity through modular organization.
Data Source
AI summary
Systems, apparatuses and methods may provide for technology that includes a voltage regulator, a board assembly including a die and a circuit board electrically coupled to a first side of the die, and a thermal dissipation assembly thermally and electrically coupled to a second side of the die, wherein the thermal dissipation assembly is further electrically coupled to the voltage regulator. In one example, the thermal dissipation assembly includes a vapor chamber and the technology further includes a plurality of copper plates electrically coupled to the voltage regulator and a package substrate containing the die, wherein the plurality of copper plates are further thermally coupled to the vapor chamber.