3D Memory Source-Control Gate Over Top Source Layer for GIDL Erase
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Solution Overview
Problem
Existing three-dimensional memory devices face challenges in efficiently applying gate-induced drain leakage (GIDL) erase voltage due to the structural limitations of their design, particularly in integrating an insulated gate over a top source layer.
Innovation Solution
A three-dimensional memory device is designed with a source layer, an alternating stack of insulating and conductive layers, and a memory opening fill structure containing a memory film and a vertical semiconductor channel, along with a source-control-gate dielectric and electrode to facilitate the application of GIDL erase voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an insulated gate is integrated over a top source layer in three-dimensional memory devices, then erase efficiency is improved, but device complexity increases
Solution Approach 1:
The source-control gate electrode is nested within the alternating stack of insulating and conductive layers, specifically positioned over the top source layer. This nesting approach integrates the insulated gate structure into the existing memory device architecture without requiring separate external gate structures, thereby improving erase efficiency while minimizing additional structural complexity.
Solution Approach 2:
The patent transitions from planar gate structures to a vertical three-dimensional configuration where the source-control gate electrode is positioned in the vertical dimension over the top source layer. This dimensional change enables effective GIDL erase voltage application in the vertical field, improving erase efficiency while the gate is formed using existing vertical stacking processes.
2Reliability
If a source-control gate electrode is positioned over the top source layer, then GIDL erase voltage application is enhanced, but manufacturing complexity increases
Solution Approach 1:
The source-control gate electrode formation is merged with the existing alternating stack formation process. The gate electrode is integrated into the same manufacturing sequence that creates the insulating and conductive layers, allowing simultaneous formation of multiple structures in a unified process flow rather than requiring separate manufacturing steps.
Solution Approach 2:
The alternating stack of insulating and conductive layers serves multiple functions: it provides structural support, enables charge storage, and simultaneously forms the insulation layer for the source-control gate electrode. This multi-functionality reduces the need for additional dedicated insulation layers, simplifying the manufacturing process while enhancing GIDL erase voltage application.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables effective application of GIDL erase voltage, enhancing the erase efficiency and performance of three-dimensional memory devices by optimizing the structural integration of the insulated gate.
Implementation Method 1
a source-control electrode located over the source-control-gate dielectric and configured to apply a gate-induced drain leakage (GIDL) erase voltage
Data Source
AI summary
A memory device includes a source layer, an alternating stack of insulating layers and electrically conductive layers located over a proximal horizontal surface of the source layer, a memory opening vertically extending through the alternating stack, a memory opening fill structure located in the memory opening and containing a memory film and a vertical semiconductor channel, a source-control-gate dielectric located over a distal horizontal surface of the source layer which is opposite to the proximal surface of the source layer, and a source-control electrode located over the source-control-gate dielectric.