Top Via Interconnect Layout Without Barrier Metal for Low RC Delay
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Solution Overview
Problem
At back end of line (BEOL) pitch scales below 30 nanometers, the resistance-capacitance product (RC) is high, leading to unsustainable RC delay, and top via integration schemes face challenges with line wiggling due to metal interconnect materials like ruthenium (Ru) and cobalt (Co), which are exacerbated by the presence of barrier metals.
Innovation Solution
A method is developed that uses a high modulus template, such as titanium nitride (TiN), to eliminate the barrier metal between the via and the upper metal line, reducing line wiggling and capacitance by maximizing metal volume and replacing the high modulus template with a low-κ dielectric that minimizes reactive-ion etching (RIE) damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If barrier metal is used between via and upper metal line, then via resistance is reduced and metal diffusion is prevented, but line wiggling increases and capacitance increases
Solution Approach 1:
The patent removes the barrier metal layer from between the via and upper metal line, extracting only the necessary portions of barrier metal (at the via sidewalls) while eliminating the harmful capacitance and line wiggling caused by complete barrier metal coverage. This selective removal resolves the contradiction by maintaining essential barrier functions while eliminating harmful effects.
Solution Approach 2:
The patent applies barrier metal selectively - present at via sidewalls to prevent diffusion but absent from the via fill region to reduce capacitance. This local differentiation of barrier metal presence resolves the contradiction by providing barrier protection only where diffusion occurs while eliminating capacitance where metal-to-metal contact is desired.
2Reliability
If barrier metal is used between via and upper metal line, then metal diffusion is prevented, but overall capacitance increases
Solution Approach 1:
The patent extracts barrier metal from the via fill region while retaining it at via sidewalls, removing the capacitive coupling between via metal and upper line metal while preserving the diffusion barrier function. This resolves the contradiction by eliminating the energy-storing capacitor formed by barrier metal while maintaining protection against metal diffusion.
3Object-generated harmful factors
If high modulus template is used, then line wiggling is reduced, but template removal complexity increases
Solution Approach 1:
The patent introduces a sacrificial mandrel as an intermediary structure that simplifies template removal. The mandrel is deposited, patterned, and removed in controlled steps, providing a systematic approach to eliminating the high modulus template without causing line wiggling. This resolves the contradiction by creating a structured removal process that maintains line integrity while eliminating the template.
4Reliability
If metal volume is maximized in via, then via resistance is reduced, but line wiggling increases
Solution Approach 1:
The patent removes barrier metal from the via fill region, allowing maximum metal volume to be deposited without the capacitive coupling that causes line wiggling. This resolves the contradiction by enabling full via fill for low resistance while eliminating the barrier metal-induced capacitance that would cause line wiggling.
Data Source
AI summary
Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A high modulus material layer is formed on a conductive stack. A trench is formed that exposes a surface of the liner and filled with metal. The metal is patterned to form interconnect lines and vias. The high modulus material is removed. A conformal layer is formed on exposed surfaces of the stack and the interconnect lines and vias. A low-κ dielectric is formed on the conformal layer such that the low-κ dielectric is of a height coplanar with the top surface of the vias. The conformal layer is removed from a top surface of the vias. A next level metal layer is formed on the top surface of the vias and low-κ dielectric layer such that added vias of the next level metal layer are directly on the top surface of the vias.