Top Via Etch-Stop Structure for Zero Line End Extension
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Solution Overview
Problem
Current semiconductor fabrication techniques face challenges in reducing line end extensions in interconnect vias, particularly at small dimensions, which limits component size reduction and interconnect density due to finite line end extensions and misalignment issues in top-via integration schemes.
Innovation Solution
The method involves forming a cut cavity in a dielectric material with an etch stop material to minimize line end extensions by embedding the cut in the dielectric prior to trench formation, allowing for self-alignment and zero line end extensions through a top-via approach, using different dielectric materials for selective etching and metal deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional dual damascene or top via processes are used, then interconnect structures can be formed, but line end extensions are finite and misalignment issues occur, limiting component size reduction and interconnect density
Solution Approach 1:
The patent applies preliminary action by forming the cut cavity and filling it with etch stop material before trench formation and metal deposition. This pre-positioned etch stop structure enables self-alignment during subsequent etching processes, ensuring that lines are precisely positioned relative to vias without requiring additional alignment margins, thereby achieving zero line end extension and maximizing interconnect density
Solution Approach 2:
The patent introduces an intermediary etch stop material that acts as a mediator between the dielectric layer and the metal interconnect structure. This intermediary layer provides a reference plane for self-alignment during etching, enabling precise positioning of lines relative to vias and eliminating the need for finite line end extensions, thus resolving the contradiction between manufacturing precision and interconnect density
2Area of stationary object
If line end extensions are reduced to minimize area, then chip area is reduced, but alignment between lines and vias becomes more critical and difficult to achieve
Solution Approach 1:
The patent applies self-service by designing a process where the etch stop material structure itself provides the alignment reference. The self-aligned trench formation process uses the pre-formed cut cavity and etch stop material as the reference, enabling the structure to self-correct alignment during etching without requiring external alignment marks or processes, thus achieving zero line end extension while maintaining manufacturing feasibility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the reduction of line end extensions to zero, even with misalignment, allowing for increased interconnect density and reduced chip area, thereby addressing the limitations of traditional dual damascene and cut solutions in advanced node scaling.
Implementation Method 1
a second dielectric material is deposited over the cut cavity to fill the line cut
Implementation Method 2
etched and patterned using reactive ion etching (RIE) techniques
Data Source
AI summary
An interconnect structure including a top via with a minimum line end extension comprises a cut filled with an etch stop material. The interconnect structure further comprises a line formed adjacent to the etch stop material. The interconnect structure further comprises a top via formed on the line adjacent to the etch stop material, wherein the top via utilizes the etch stop material to achieve minimum line extension.