Top Via Interconnect Texture Suppression Layers
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Solution Overview
Problem
In integrated circuit fabrication, particularly in the back end of line (BEOL) process, sub-15 nanometer critical dimension dual damascene interconnects face challenges such as voids, roughness, and resistance variability due to large copper grains and restricted geometry, which affect the reliability and dimensional control of metal lines and top vias.
Innovation Solution
The implementation of alternating layers of conductor and texture suppression layers, where the texture suppression layers are thinner and have similar resistivity to the conductor layers, is used to control grain size and surface roughness, preventing uncontrolled void growth and ensuring precise dimensional control in metal lines and top vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper is used as the conductor material in sub-15 nanometer dual damascene interconnects, then electrical conductivity is improved, but large copper grains cause voids, roughness, and resistance variability
Solution Approach 1:
The patent segments the conductor layer into multiple thin alternating layers of first metal (e.g., copper) and second metal (e.g., ruthenium or cobalt). This segmentation prevents the formation of large copper grains by limiting the vertical growth of copper, thereby eliminating voids and reducing surface roughness while maintaining electrical conductivity through the conductive metal layers.
Solution Approach 2:
The patent employs a composite interconnect structure consisting of alternating layers of conductive metal (first metal) and texture suppression metal (second metal). This composite structure combines the high conductivity of copper with the grain-growing suppression properties of metals like ruthenium or cobalt, achieving both electrical performance and dimensional control.
2Manufacturing precision
If the metal layers are made thinner to improve dimensional control, then manufacturing precision is improved, but the conductor layers become too thin to maintain low resistance
Solution Approach 1:
The conductor layer is segmented into multiple thin alternating layers of conductive metal and texture suppression metal. Each layer is thin enough to maintain dimensional control, but the stacked structure provides sufficient total conductivity. The segmentation allows precise thickness control of each layer while achieving low overall resistance through the cumulative effect of multiple conductive layers.
Solution Approach 2:
The patent changes the physical parameters of the metal layers by controlling the thickness of each alternating layer. The first metal layers are made thin (e.g., 2-5 nm) to prevent grain growth and control roughness, while the second metal layers are even thinner (e.g., 0.5-2 nm) to suppress texture without adding significant resistance. This parameter optimization balances dimensional control with electrical performance.
3Manufacturing precision
If alternating layers of conductor and texture suppression metals are used, then surface roughness and void formation are reduced, but the device structure becomes more complex
Solution Approach 1:
The interconnect structure is segmented into alternating layers of conductor metal and texture suppression metal, deposited in sequence using standard sputtering or atomic layer deposition equipment. While the structure has multiple layers, the fabrication process remains compatible with existing manufacturing tools and techniques, managing complexity through process integration rather than requiring entirely new fabrication methods.
Data Source
AI summary
An interconnect structure and a method of forming the interconnect structure are provided. The interconnect structure includes a metal line layer and a top via layer that each include a plurality of alternating first layers composed of a first metal and second layers composed of a second metal, whereby the second layers are thinner than the first layers.