Top Via Interconnect Structure With Reduced Line Bottom Dimension
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Solution Overview
Problem
In integrated circuit (IC) fabrication, the bottom dimension of conductive lines in interconnect structures is often larger than desired, leading to potential dielectric breakdown and short-circuiting issues, which limits the maximum applied voltage and increases the risk of electrical failures.
Innovation Solution
A top via interconnect structure is formed with a conductive line having a reduced bottom dimension, achieved by using an etch stop layer with higher dielectric breakdown than the surrounding materials, which confines the line bottom dimension through selective etching and spacer material deposition, allowing for smaller trench dimensions without altering lithography or etch procedures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the bottom dimension of conductive lines is reduced to prevent dielectric breakdown, then dielectric breakdown resistance is improved, but manufacturing complexity increases due to additional process steps
Solution Approach 1:
An etch stop layer is deposited beforehand on the conductive via before forming the conductive line. This preliminary action creates a predefined boundary that automatically limits the bottom dimension of the conductive line during subsequent etching processes, eliminating the need for complex multi-step dimension control procedures
Solution Approach 2:
The etch stop layer acts as an intermediary element between the conductive via and the conductive line. It mediates the dimension control by providing a physical barrier that stops the etching process at the desired depth, thereby controlling the bottom dimension of the conductive line without requiring direct intervention in the line formation process
2Manufacturing precision
If spacer material is deposited to control line bottom dimension, then manufacturing precision is improved, but device complexity increases due to additional materials and steps
Solution Approach 1:
The etch stop layer provides self-service dimension control by automatically stopping the etching process when it reaches the layer. This self-limiting mechanism eliminates the need for precise control of spacer material thickness or complex etch depth control procedures, achieving dimension control through the inherent properties of the etch stop layer
3Ease of manufacture
If larger line bottom dimension is used, then ease of manufacture is improved, but reliability deteriorates due to increased dielectric breakdown risk
Solution Approach 1:
The etch stop layer creates local quality differentiation by providing a distinct boundary layer at the via interface. This local structural variation enables precise control of the line bottom dimension only where needed (at the via interface), while maintaining standard manufacturing processes for the rest of the line formation
Solution Approach 2:
By depositing the etch stop layer in advance, the structure is prepared to automatically limit the line bottom dimension during standard etching processes. This preliminary preparation maintains ease of manufacture by using conventional etching steps while inherently preventing excessive line bottom dimension growth
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The reduced line bottom dimension enhances time-dependent dielectric breakdown resistance, decreases the potential for short-circuiting, and allows for higher maximum applied voltage without changing existing fabrication processes, thereby improving the reliability and performance of IC interconnects.
Implementation Method 1
achieved by using an etch stop layer with higher dielectric breakdown than the surrounding materials, which confines the line bottom dimension through selective etching
Data Source
AI summary
A technique relates to an integrated circuit (IC). The IC includes a conductive line formed on a conductive via, the conductive line being formed though a dielectric material. The IC includes an etch stop layer having one or more extended portions intervening between one or more edge portions of the conductive line and the conductive via, the one or more edge portions being at a periphery of the conductive line and the conductive via, the etch stop layer including a higher dielectric breakdown than the dielectric material. The one or more extended portions of the etch stop layer cause the conductive line to be formed with a bottom part having a reduced dimension than an upper part of the conductive line.