Top Via Seed Layer for Selective Interconnect Line Growth
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Solution Overview
Problem
The challenge in semiconductor fabrication lies in the selective growth of interconnect lines and vias, particularly due to the small exposed metal area of metallic vias, which complicates the formation of intricate structures within increasingly smaller wafer footprints, requiring advanced processes like phase-shifting and optical proximity correction to achieve line-to-line pitches below 30 nm.
Innovation Solution
A conductive thin metal layer, referred to as a seed layer, is deposited above a via to act as a template for the selective growth of metal lines above the via, enabling high-quality gap-filling and reducing barrier liner thicknesses, allowing for non-damascene-based processes that do not require metal planarization, thereby facilitating the integration of top vias and lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional interconnect formation processes are used, then manufacturing simplicity is maintained, but selective growth of interconnect lines is difficult due to small exposed metal area of vias
Solution Approach 1:
A seed layer is deposited over the via structure before the interconnect line formation. This preliminary action creates a controlled template that enables selective growth of the interconnect line only where needed, solving the problem of small exposed metal area by providing a pre-formed growth template.
Solution Approach 2:
The seed layer acts as an intermediary between the via structure and the interconnect line. It mediates the formation process by providing a controlled interface that enables precise selective growth while simplifying the overall manufacturing process.
2Reliability
If barrier liner thicknesses are reduced, then resistance and capacitance of interconnect lines are improved, but gap-filling quality becomes more difficult to achieve
Solution Approach 1:
The seed layer is deposited in advance to create a uniform template that guides subsequent material deposition. This preliminary structure ensures that even with reduced barrier liner thicknesses, the gap-filling process achieves uniform and defect-free results by following the pre-established seed layer geometry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the selective growth of interconnect lines with improved resistance and capacitance, reducing manufacturing complexity and costs by promoting uniform, defect-free gap-filling and allowing for the use of non-damascene-based processes, enhancing the integration of top vias and lines within smaller semiconductor structures.
Implementation Method 1
a second conductive line is deposited onto the exposed surface of the seed layer
Data Source
AI summary
Embodiments of the present invention are directed to fabrication methods and resulting interconnect structures having a conductive thin metal layer on a top via that promotes the selective growth of the next level interconnect lines (the line above). In a non-limiting embodiment of the invention, a first conductive line is formed in a dielectric layer. A via is formed on the first conductive line and a seed layer is formed on the via and the dielectric layer. A surface of the seed layer is exposed and a second conductive line is deposited onto the exposed surface of the seed layer. In a non-limiting embodiment of the invention, the second conductive line is selectively grown from the seed layer.