Top Via Stack Metallization for Interconnect Resistance
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Solution Overview
Problem
High interconnect line resistance is a major limiting factor in achieving favorable device performance in advanced technology nodes, particularly due to the challenge of copper diffusion into silicon-based FEOL devices in semiconductor manufacturing, which can cause shorting and alter transistor characteristics.
Innovation Solution
The method involves forming metallization layers with conductive lines of varying heights, selectively recessing certain lines, depositing dielectric layers, and creating via layers to expose top surfaces of conductive lines, allowing for the deposition of conductive materials that reduce resistance by optimizing metal line configurations within a given metallization level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper is used as the bulk conductor material in BEOL interconnects, then electrical conductivity is improved, but copper diffusion into FEOL silicon-based devices causes shorting and alters transistor characteristics
Solution Approach 1:
The patent introduces a middle-of-line (MOL) interconnect layer with diffusion barrier materials (such as tantalum, tungsten, or cobalt) positioned between the copper-based BEOL interconnects and the silicon-based FEOL devices. This intermediary layer prevents copper diffusion into the silicon devices while maintaining electrical connectivity, thereby resolving the contradiction between achieving high conductivity and preventing harmful diffusion.
2Reliability
If traditional planar metallization layers are used, then manufacturing simplicity is maintained, but interconnect line resistance becomes a major limiting factor in device performance
Solution Approach 1:
The patent transitions from traditional planar (2D) metallization layers to three-dimensional (3D) vertical interconnect structures. By forming vias that extend vertically through dielectric layers and creating stacked metallization configurations, the patent reduces current path length and interconnect resistance, thereby improving device performance while managing the complexity of additional manufacturing steps.
3Loss of energy
If metallization layers with varying line heights are implemented, then resistance is decreased through optimized metal line configurations, but manufacturing complexity increases
Solution Approach 1:
The patent implements selective recessing of conductive lines in specific regions where resistance optimization is needed, rather than uniformly modifying the entire metallization layer. This allows for locally optimized interconnect structures with varying heights and configurations in high-current-density areas, while maintaining standard planar structures in other regions, thereby balancing performance improvement with manufacturing feasibility.
4Reliability
If via layers are formed to expose top surfaces of conductive lines for material deposition, then electrical connectivity and resistance reduction are achieved, but the number of fabrication steps increases
Solution Approach 1:
The patent performs preliminary planarization and via formation steps early in the fabrication sequence, before subsequent metallization and dielectric deposition steps. By preparing the via structures and exposing conductive line surfaces in advance, the patent enables more efficient material deposition and reduces the need for rework or additional alignment steps, thereby mitigating the impact of increased fabrication complexity on overall productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly decreases interconnect line resistance, enabling improved device performance by allowing for taller metal lines and more efficient integration of functions on a single chip, thereby addressing the limitations of copper diffusion and enhancing semiconductor device reliability.
Implementation Method 1
depositing a second dielectric layer in the recessed portion of the second conductive line and on a top surface of the first conductive line
Implementation Method 2
depositing a first conductive material in the first via
Data Source
AI summary
A semiconductor structure includes a first metallization layer disposed on a first etch stop layer. The first metallization layer includes a first conductive line and a second conductive line, each disposed in a first dielectric layer and extending from the first etch stop layer. The height of the first conductive line is greater than a height of the second conductive line. The semiconductor structure further includes a first via layer comprising a second dielectric layer disposed on a top surface of the first metallization layer and a first via and a second via in the second dielectric layer. The semiconductor structure further includes a first conductive material disposed on a top surface of the first conductive line in the first via. The semiconductor structure further includes a second conductive material disposed on a top surface of the second conductive line in the second via.