Top-Via Trim Method for Semiconductor Interconnect Alignment
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Solution Overview
Problem
Patterning misalignments in semiconductor devices lead to reduced level-to-level contact area and increased via resistance in top-via structures, which is undesirable.
Innovation Solution
Employing a top-via trim methodology using subtractive etch or damascene processes to achieve fully-aligned top-via interconnects by trimming vias after constructing multi-level structures, ensuring accurate alignment and minimizing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic processes are used to form vias, then the manufacturing process is simple and straightforward, but patterning misalignments occur that reduce level-to-level contact area and increase via resistance
Solution Approach 1:
The patent applies preliminary action by forming an extended mandrel structure that protrudes beyond the via opening boundaries before etching. This extended mandrel serves as a pre-positioned alignment reference that ensures the via will be correctly positioned relative to lower interconnect levels, even if subsequent lithographic steps experience misalignment. The mandrel is formed in advance with precise positioning, and this pre-established structure guides the via formation process to achieve better alignment precision.
Solution Approach 2:
The patent introduces an intermediary element - the extended mandrel - that mediates between the lithographic patterning process and the final via structure. This mandrel acts as a bridge or reference structure that transfers alignment information from the lithography step to the via formation step, ensuring that the via is properly aligned with lower interconnect levels despite variations in the lithographic process.
2Reliability
If via openings are etched directly without extended mandrels, then the process is simpler, but via resistance increases due to reduced contact area from misalignment
Solution Approach 1:
The extended mandrel is formed in advance as a preliminary structure that defines the precise location and dimensions of the via opening. By establishing this reference structure before etching the via, the patent ensures that the via will have optimal alignment and contact area with lower interconnect levels, improving via connection reliability and reducing via resistance.
Solution Approach 2:
The extended mandrel serves as an intermediary reference structure that mediates between the lithographic patterning and the via etching processes. It provides a stable, pre-positioned template that ensures consistent via placement and dimensions, leading to improved alignment and reduced via resistance without requiring complex real-time adjustment mechanisms.
3Manufacturing precision
If extended mandrels are used to improve via alignment, then via resistance decreases due to better alignment, but the manufacturing process becomes more complex
Solution Approach 1:
The extended mandrel is created as a preliminary structure during the interconnect formation process itself, utilizing the same lithographic and etching steps that form the interconnect lines. This approach integrates the alignment reference creation into the existing manufacturing flow rather than adding separate dedicated steps, thereby improving via alignment precision while minimizing the increase in overall process complexity.
Solution Approach 2:
The extended mandrel serves multiple functions: it acts as a structural element of the interconnect, provides an alignment reference for via formation, and defines the via opening boundaries. By making this single structure multi-functional, the patent achieves improved via alignment without requiring additional dedicated reference structures or complex process steps.
Data Source
AI summary
A method is presented for constructing fully-aligned top-via interconnects by employing a subtractive etch process. The method includes building a first metallization stack over a substrate, depositing a first lithography stack over the first metallization stack, etching the first lithography stack and the first metallization stack to form a receded first metallization stack, and depositing a first dielectric adjacent the receded first metallization stack. The method further includes building a second metallization stack over the first dielectric and the receded first metallization stack, depositing a second lithography stack over the second metallization stack, etching the second lithography stack and the second metallization stack to form a receded second metallization stack, and trimming the receded first metallization stack to form a via connecting the receded first metallization stack to the receded second metallization stack.