TOPCon Solar Cell Rear Texture for Uniform Tunnel Oxide
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Solution Overview
Problem
The manufacturing of N-type tunnel oxide passivated contact (TOPCon) solar cells faces challenges in removing borosilicate glass, leading to increased contact resistivity and fluctuations in fill factor, which affects the photoelectric conversion efficiency due to the difficulty in polishing the rear surface structure.
Innovation Solution
A solar cell design with a first texture structure on the rear surface and a pyramid-shaped microstructure on the front surface, along with specific passivation layers, is implemented to improve open-circuit voltage and reduce contact resistance, featuring a method that includes alkali polishing and chemical vapor deposition to form tunnel oxide layers with controlled thickness and uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If borosilicate glass is formed by boron diffusion on the rear surface of the silicon wafer, then the tunnel oxide passivated contact (TOPCon) structure is achieved, but the glass is more difficult to remove compared with phosphorosilicate glass, leading to increased manufacturing complexity and contact resistivity
Solution Approach 1:
The patent extracts and removes the borosilicate glass layer from the rear surface using a specifically formulated etching solution containing hydrofluoric acid, nitric acid, and acetic acid. This extraction process eliminates the harmful glass layer that would otherwise interfere with subsequent tunnel oxide formation and increase contact resistivity, while preserving the underlying silicon substrate for effective passivation.
Solution Approach 2:
The patent changes the chemical parameters of the etching solution by using a specific composition ratio of hydrofluoric acid, nitric acid, and acetic acid, along with controlling temperature and etching time parameters. This parameter optimization enables selective removal of borosilicate glass while minimizing damage to the silicon substrate, resolving the contradiction between effective glass removal and substrate preservation.
2Manufacturing precision
If the rear surface is polished with acid additives to achieve a flat structure, then the surface is cleaned and prepared, but the polished structure directly affects the manufacturing of the tunnel oxide layer and polycrystalline silicon layer, leading to fluctuations in fill factor and contact resistivity
Solution Approach 1:
The patent applies local quality by creating a selectively textured rear surface rather than a uniformly flat surface. The etching process produces localized microstructures with different morphologies in different regions, allowing areas with appropriate texture to enhance light trapping and carrier collection while maintaining stable electrical contact properties. This local differentiation resolves the contradiction between surface preparation and electrical stability.
Solution Approach 2:
The patent introduces curved and textured surface structures on the rear surface through controlled etching, replacing the conventional flat polished surface. The curved microstructures enhance light trapping efficiency and create favorable conditions for tunnel oxide formation, while the textured surface morphology stabilizes the fill factor and contact resistivity by providing consistent electrical contact across the metal paste application area.
3Ease of manufacture
If the distance between top surfaces of stacked first substructures is greater than 2 μm or the one-dimensional size exceeds 45 μm, then the texture structure is easier to form, but the uniformity of the tunnel oxide layer deteriorates and photoelectric conversion efficiency decreases
Solution Approach 1:
The patent optimizes the geometric parameters of the texture structure by controlling the distance between top surfaces of stacked substructures to be ≤2 μm and the one-dimensional size to be ≤45 μm. These parameter specifications ensure that the subsequent tunnel oxide layer deposition process produces uniform oxide thickness across the textured surface, enabling effective tunneling current while maintaining high photoelectric conversion efficiency.
Solution Approach 2:
The patent applies a more stringent texture structure configuration than conventionally required, with tighter control on substructure spacing and size. This excessive precision in texture formation ensures that even in the presence of manufacturing variations, the tunnel oxide layer maintains sufficient uniformity for effective device operation, resolving the contradiction between manufacturing ease and oxide layer quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the uniformity of the tunnel oxide layer, reduces contact resistivity, and improves the photoelectric conversion efficiency by optimizing the texture structures and passivation layers on both surfaces of the solar cell.
Implementation Method 1
Generally, borosilicate glass on a rear surface of an N-type solar cell is removed by an oxidizing mixed acid solution
Implementation Method 2
an N-type tunnel oxide passivated contact (TOPCon) solar cell relies on a 'tunnel effect' to achieve passivated contact on a rear surface of the solar cell
Implementation Method 3
a rear surface of the semiconductor substrate has a first texture structure, the first texture structure includes two or more first substructures at least partially stacked on one another
Implementation Method 4
a front surface of the semiconductor substrate has a second texture structure, the second texture structure includes a pyramid-shaped microstructure
Data Source
AI summary
Provided are a solar cell, a manufacturing method thereof, and a photovoltaic module. The solar cell includes: a semiconductor substrate, in which a rear surface of the semiconductor substrate having a first texture structure, the first texture structure includes two or more first substructures at least partially stacked on one another, and in a direction away from the rear surface and perpendicular to the rear surface, a distance between a top surface of an outermost first substructure and a top surface of an adjacent first substructure being less than or equal to 2 μm; a first passivation layer located on a front surface of the semiconductor substrate; a tunnel oxide layer located on the first texture structure; a doped conductive layer located on a surface of the tunnel oxide layer; and a second passivation layer located on a surface of the doped conductive layer.