Topmost Metal Layer Openings for Hydrogen Diffusion in DRAM
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Solution Overview
Problem
In semiconductor devices like DRAM, high leakage current through cell transistors leads to increased power consumption and reduced refresh cycle times due to interface trap density and channel length issues, which are exacerbated by the use of a planar topmost metal layer that blocks hydrogen atoms from reaching the gate insulating layer during the hydrogen alloy process.
Innovation Solution
A semiconductor device with a topmost metal layer having openings over the cell array region, allowing hydrogen atoms to reach the interface between the gate insulating layer and the substrate, thereby reducing interface trap density and improving leakage current characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a planar topmost metal layer is used to cover the cell array region, then voltage drop due to power line resistance is minimized, but hydrogen atoms cannot reach the gate insulating layer interface during the hydrogen alloy process
Solution Approach 1:
The topmost metal layer is segmented by forming openings (contact holes) through it, allowing the metal layer to be divided into multiple regions. This segmentation enables hydrogen atoms to reach the gate insulating layer interface at specific locations while maintaining the overall continuity and low resistance of the power line network.
Solution Approach 2:
The topmost metal layer is designed with different properties in different regions: in most areas it provides low resistance power distribution, while in specific regions (where openings are formed) it allows hydrogen diffusion to reduce interface trap density. This local differentiation resolves the contradiction between maintaining low voltage drop and enabling hydrogen access.
2Productivity
If the cell transistor channel length is decreased to improve integration density, then more cells can be packed, but leakage current increases due to interface trap density
Solution Approach 1:
The hydrogen alloy process is performed before forming the topmost metal layer, allowing hydrogen atoms to reach and passivate interface traps at the gate insulating layer interface in advance. This preliminary action reduces interface trap density and leakage current before the metal layer is deposited, enabling subsequent miniaturization without proportionally increasing leakage.
3Ease of manufacture
If the hydrogen alloy process is performed after formation of a planar topmost metal layer, then the process sequence is simplified, but hydrogen atoms are blocked from reaching the gate insulating layer interface
Solution Approach 1:
The hydrogen alloy process is performed at an earlier stage in the fabrication sequence, before the topmost metal layer is formed. This preliminary timing allows hydrogen atoms to access the gate insulating layer interface effectively. The topmost metal layer is then formed afterward with openings that maintain both the low resistance power distribution and enable hydrogen diffusion paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The openings in the topmost metal layer enhance the diffusion of hydrogen atoms, significantly decreasing interface trap density and improving the refresh cycle time and production yield of DRAM devices by reducing leakage current.
Implementation Method 1
The openings in the topmost metal layer enhance the diffusion of hydrogen atoms, significantly decreasing interface trap density
Data Source
AI summary
In one embodiment, a semiconductor device has a topmost or highest conductive layer with at least one opening. The semiconductor device includes a semiconductor substrate having a cell array region and an interlayer insulating layer covering the substrate having the cell array region. The topmost conductive layer is disposed on the interlayer insulating layer in the cell array region. The topmost conductive layer has at least one opening. A method of fabricating the semiconductor device is also provided. The openings penetrating the topmost metal layer help hydrogen atoms reach the interfaces of gate insulating layers of cell MOS transistors and/or peripheral MOS transistors during a metal alloy process, thereby improve a performance (production yield and/or refresh characteristics) of a memory device.