Topographical Feature for Polymer Thickness Enhancement in Semiconductor Interconnects
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Solution Overview
Problem
The high mismatch in coefficients of thermal expansion between solder bumps, semiconductor dies, and chip package substrates leads to thermal stresses and potential breakage of back-end-of-the-line material due to rotational forces during thermal cycling, especially at the edges and corners of solder bumps.
Innovation Solution
A topographical feature is introduced on the semiconductor die surface near the conductive bond pads, creating a gap that enhances the thickness of the non-conductive layer, providing a stress buffer and preventing breakage by increasing the localized thickness of the polymer layer underneath the solder bumps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the non-conductive layer thickness is increased to provide stress buffering, then reliability improves, but device complexity increases
Solution Approach 1:
The patent applies local quality by creating a topographical feature that locally increases the non-conductive layer thickness only in specific high-stress areas (under and around solder bumps), rather than uniformly increasing thickness across the entire die. This localized approach provides stress buffering where needed while avoiding unnecessary complexity and material usage in low-stress regions.
Solution Approach 2:
The patent introduces a vertical dimensionality change by forming a topographical feature (such as a raised ridge or mound) on the die surface. This three-dimensional structure allows the non-conductive layer to have variable thickness, creating an enhanced stress buffer zone vertically under the solder bumps without increasing the lateral footprint or overall device complexity.
2Stress or pressure
If the non-conductive layer thickness is enhanced locally, then thermal stress resistance improves, but manufacturing precision requirements increase
Solution Approach 1:
The topographical feature is formed preliminarily on the die surface before the non-conductive layer is deposited. This preliminary action creates a predetermined template that guides the subsequent non-conductive layer formation, ensuring that the enhanced thickness occurs automatically in the correct location under the solder bumps without requiring complex real-time control during layer deposition.
Solution Approach 2:
The topographical feature serves as a beforehand cushioning structure that pre-positioned stress buffer material in high-stress areas. By creating this feature in advance, the design anticipates thermal stress locations and provides protective thickness enhancement before the actual thermal cycling occurs, reducing the need for precise post-adjustment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The enhanced thickness of the non-conductive layer effectively reduces thermal stresses at high-stress areas, preventing breakage of the back-end-of-the-line material while maintaining sufficient stress buffering across the semiconductor die.
Implementation Method 1
there is a high degree of mismatch between the coefficients of thermal expansion (CTE) between the solder bumps, the semiconductor die and the semiconductor chip package substrate. The mismatch of CTE results in the formation of large strains that cause thermal stresses to develop about the solder bumps and the semiconductor die during thermal cycling
Data Source
AI summary
A topographical feature is formed proximate to a conductive bond pad that is used to couple a solder bump to a semiconductor die. The topographical feature is separated from the conductive bond pad by a gap. In one embodiment, the topographical feature is formed at a location that is slightly beyond the perimeter of the solder bump, wherein an edge of the bump is aligned vertically to coincide with the gap separating the conductive bond pad from the topographical feature. The topographical feature provides thickness enhancement of a non-conductive layer disposed over the semiconductor die and the conductive bond pad and stress buffering.