Semiconductor Topography Matching via Weighted Layout Correlation
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Solution Overview
Problem
In semiconductor manufacturing, accurately matching surface topography measurements to circuit layouts is time-consuming and challenging due to the lack of efficient methods for identifying the correct measurement straight line paths, hindering the accuracy of circuit patterning and model training.
Innovation Solution
A processing device and method that converts original surface topography curves into surface topography variation curves and conductor density variation curves, analyzing weighted correlations to determine the matching measurement straight line path from layout straight-line paths, thereby reducing the need for extensive calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional surface topography measurement matching methods are used, then measurement accuracy can be achieved, but significant time is required for location correction and matching
Solution Approach 1:
The patent applies preliminary action by pre-processing the original surface topography curve into a processed surface topography curve with enhanced features before matching. The system performs preliminary conversion of the topography data to highlight key characteristics, so that when matching is required, the processed curve enables faster and more accurate location identification without extensive real-time correction
Solution Approach 2:
The patent changes parameters by transforming the original surface topography curve into a processed version with modified characteristics. The processing converts the raw measurement data into a form with enhanced distinguishable features, changing the parameter representation to facilitate quicker and more accurate matching with circuit layout locations
2Measurement precision
If extensive calibration and correction are performed to match measurement locations with circuit layout, then matching accuracy improves, but processing time and complexity increase
Solution Approach 1:
The patent applies taking out by extracting key characteristic features from the original surface topography curve to create a processed curve that retains essential matching information while removing unnecessary complexity. This extraction process isolates the critical topography features needed for accurate matching, simplifying the overall processing requirements
Solution Approach 2:
The system performs preliminary processing of the surface topography data to pre-enhance matching features before the actual matching operation. This advance preparation reduces the complexity of subsequent matching operations by having the data ready in an optimized format
Data Source
AI summary
A matching method for semiconductor topography measurement and a processing device using the same are provided. The matching method includes the following steps. An original surface topography curve is obtained. The original surface topography curve is obtained by measuring along a measurement straight line path of a semiconductor device. The original surface topography curve is converted into a surface topography variation curve. A circuit layout is obtained. A plurality of conductor density variation curves are obtained along a plurality of layout straight-line paths. According to a plurality of weighted values of a plurality of topography variation observation intervals of the surface topography variation curve, a weighted correlation between the surface topography variation curve and each of the conductor density variation curves is analyzed. According to the weighted correlations, the measurement straight line path matching the original surface topography curve is obtained from the layout straight-line paths.