Topological Diagrams for Mask Alignment Conflict Resolution
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Advanced semiconductor technologies face challenges in maintaining critical dimension (CD) and trench end resolution due to high aspect ratios in patterned photoresist layers, particularly with multiple patterning methods where mask alignment conflicts occur, affecting manufacturing yield and alignment between layers.
Innovation Solution
A method and system for effective IC design and fabrication using a decomposable checking approach for mask alignment, which involves converting IC design layouts into topological diagrams with nodes, chains, and arrows to optimize layer-to-layer alignment, applying rules based on loop and path count to identify and resolve mask alignment conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple patterning is used to enhance lithography patterning resolution, then feature size reduction is achieved, but mask alignment conflicts occur between different layers
Solution Approach 1:
The patent segments the mask alignment checking process into multiple independent checks: intra-layer alignment checking and inter-layer alignment checking. Each layer is first checked for internal alignment consistency, then layers are checked for mutual alignment. This segmentation allows systematic identification and resolution of alignment conflicts without overwhelming complexity.
Solution Approach 2:
The patent performs preliminary alignment checking before actual mask fabrication and patterning processes. By identifying alignment conflicts in the design stage through topological diagram analysis, the method enables preventive measures to be taken, such as design modifications or process adjustments, before manufacturing issues arise.
2Manufacturing precision
If high aspect ratio photoresist layers are used for small feature sizes, then critical dimension control becomes difficult, but maintaining desired CD is essential
Solution Approach 1:
The patent introduces topological diagrams as an intermediary representation between the physical photoresist structures and the alignment checking process. These diagrams abstract the complex 3D high aspect ratio structures into simplified 2D topological representations that capture essential alignment relationships, making the checking process manageable despite the complexity of the actual photoresist layers.
3Reliability
If manual engineer intervention is used for mask alignment optimization, then alignment conflicts can be resolved, but design cycles become longer
Solution Approach 1:
The patent implements self-service through automated alignment checking and conflict identification. The system automatically generates topological diagrams, performs alignment checks, identifies conflicts, and provides suggested resolutions without requiring manual engineer intervention for each step. This automation significantly reduces the time required compared to manual analysis while maintaining reliable alignment optimization.
Data Source
AI summary
The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a first plurality of features defined in a first layer and a second plurality of features defined in a second layer; converting the IC design layout to a topological diagram having nodes, chains and arrows; and identifying alignment conflict based on the topological diagram using rules associated with loop and path count.