Topological Semimetal Interconnects for Low-Resistance BEOL Scaling
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Solution Overview
Problem
As interconnect dimensions shrink beyond the 7 nm node, copper (Cu) interconnects experience significant increases in line resistance due to grain-boundary and surface-roughness scattering, limiting circuit performance, and alternative materials like topological insulators have low carrier densities, making integration impractical.
Innovation Solution
The use of topological semi-metal materials, such as Weyl semi-metals and multifold fermion systems, which exhibit improved resistivity size effects and high carrier densities, are integrated as back-end-of-line (BEOL) interconnects, featuring bulk band-crossings and robust surface states that reduce resistance-area product with decreasing thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper interconnects are used at dimensions beyond 7 nm node, then manufacturing process is well-established and ease of manufacture is maintained, but line resistance increases significantly due to grain-boundary and surface-roughness scattering
Solution Approach 1:
The patent changes the material parameter from conventional copper to topological semi-metal materials, which fundamentally alters the electrical transport properties. This material substitution resolves the line resistance issue by providing a different physical mechanism for charge transport that is less sensitive to grain-boundary and surface-roughness scattering at small dimensions.
Solution Approach 2:
The patent employs composite material structures including topological semi-metal layers combined with dielectric layers and hermetic cap layers. This composite approach allows integration of materials with complementary properties: topological semi-metals provide low resistance, while dielectric layers provide isolation and hermetic cap layers provide protection, together solving both electrical performance and manufacturing challenges.
2Reliability
If topological insulator materials are used as alternatives to copper, then carrier density is improved, but integration practicality deteriorates due to low carrier densities making integration impractical
Solution Approach 1:
The patent changes the material class from topological insulators to topological semi-metals, which have fundamentally different electronic properties. Topological semi-metals possess high carrier densities similar to conventional metals while maintaining topologically protected surface states, thus improving carrier density without sacrificing integration practicality.
Solution Approach 2:
The patent adopts materials and processes that are compatible with existing semiconductor manufacturing infrastructure. By selecting topological semi-metal materials that can be deposited using standard techniques and integrated into existing fabrication flows, the solution maintains ease of manufacture while achieving improved electrical properties.
3Productivity
If interconnect dimensions are reduced to improve circuit density, then productivity and circuit density are improved, but line resistance increases due to scattering effects
Solution Approach 1:
The patent changes the material properties to topological semi-metals which exhibit reduced sensitivity of resistivity to dimensional scaling. The topologically protected surface states provide robust charge transport that maintains low resistance even at reduced dimensions, enabling continued circuit density improvement without the resistance penalty normally associated with scaling.
Solution Approach 2:
The patent exploits the surface states of topological semi-metals, which are two-dimensional electron systems that propagate along the surface. This surface-state transport mechanism provides a different conduction pathway that is less affected by the dimensional reduction and scattering effects that plague bulk material interconnects at small scales.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Topological semi-metal interconnects demonstrate reduced resistivity at small nodes, potentially reducing resistance-capacitance (RC) products by >50% at 5 nm and >90% at 3 nm nodes compared to copper, enhancing circuit performance and scalability.
Implementation Method 1
topological semi-metal materials, such as Weyl semi-metals and multifold fermion systems, which exhibit improved resistivity size effects and high carrier densities, are integrated as back-end-of-line (BEOL) interconnects, featuring bulk band-crossings and robust surface states that reduce resistance-area product with decreasing thickness
Data Source
AI summary
Provided is a method for fabricating an interconnect. The method comprises forming a topological semi-metal layer. The method further comprises patterning the topological semi-metal layer to form one or more interconnects. The method further comprises forming a dielectric layer between the one or more interconnects. The method further comprises forming a hermetic dielectric cap layer on top of the one or more interconnects and the dielectric layer.