Topology Discovery Instructions for Logical Partition CPU Optimization
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Solution Overview
Problem
In multi-processor systems, programs running in logical partitions lack awareness of the underlying CPU topology, leading to suboptimal resource allocation and performance due to ignorance of the internal packaging and distance between CPUs, which limits the potential of symmetric-multiprocessing configurations.
Innovation Solution
The introduction of a PERFORM TOPOLOGY FUNCTION (PTF) instruction and an enhanced STORE SYSTEM INFORMATION (STSI) instruction provides topology information, allowing programs to understand the CPU configuration and optimize resource assignment by minimizing the distance between CPUs, thereby improving performance through better cache hit ratios and reduced communication paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If programs run in logical partitions without topology awareness, then system simplicity is maintained, but resource allocation efficiency deteriorates
Solution Approach 1:
The patent introduces topology discovery instructions (STSI with function code 15, PTF instruction) as intermediaries between the program and the complex CPU topology. These instructions provide a simplified interface that automatically retrieves and presents topology information without requiring programs to directly interact with complex hardware structures, thus maintaining program simplicity while enabling efficient resource allocation decisions
Solution Approach 2:
The patent implements feedback mechanisms where topology information is continuously discovered and provided back to programs through enhanced instructions. The STSI instruction with function code 15 and PTF instruction return topology data that includes CPU distances, cache hierarchies, and packaging information, enabling programs to make informed resource allocation decisions based on actual system state
2Productivity
If topology information is provided through enhanced instructions, then resource allocation efficiency is improved, but instruction complexity increases
Solution Approach 1:
The patent enhances existing standard instructions (STSI, PTF) with additional functionality rather than creating entirely new instruction types. The STSI instruction already existed for system information retrieval; by adding function code 15, it gains topology discovery capability. Similarly, the PTF instruction is extended to include topology information in its response. This multi-functionality approach allows topology discovery using existing instruction frameworks, minimizing the increase in instruction complexity
3Productivity
If programs optimize CPU assignment based on topology, then performance is improved, but program complexity increases
Solution Approach 1:
The patent enables programs to self-service by providing them with the tools (topology discovery instructions) to automatically obtain and process topology information themselves. Rather than requiring the operating system or hardware to automatically optimize CPU assignment, the program uses the STSI and PTF instructions to discover topology and makes its own optimization decisions, reducing the need for complex external control mechanisms
Data Source
AI summary
In a logically partitioned host computer system comprising host processors (host CPUs), a facility and instruction for discovering topology of one or more guest processors (guest CPUs) of a guest configuration comprises a guest processor of the guest configuration fetching and executing a STORE SYSTEM INFORMATION instruction that obtains topology information of the computer configuration. The topology information comprising nesting information of processors of the configuration and the degree of dedication a host processor provides to a corresponding guest processor. The information is preferably stored in a single table in memory.