Topology Recognition Model Compression for IoT Power Grid Terminals

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Solution Overview

Problem

The challenge is to compress a topology recognition model for power grids while maintaining accuracy, to enable deployment on IoTIPS terminals with limited hardware resources.

Innovation Solution

The method involves pruning the model to remove redundant channels and layers, followed by quantizing the weight parameters of neural network layers to reduce bit quantity, and iteratively training and compressing the model until a compressed version is achieved that meets accuracy requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the topology recognition model is compressed to reduce model size, then the model can be deployed on IOTIPS terminals with limited hardware resources, but the measurement accuracy of the topology recognition model decreases

Engineering Contradiction:
Improvemodel sizeVSAvoidrecognition accuracy
Core Design Contradiction:
Quantity of substanceVSMeasurement precision

Solution Approach 1:

The patent segments the model compression process into two distinct phases: pruning (removing redundant neurons and connections) and quantization (reducing precision of weight parameters). This segmentation allows systematic reduction of model size while managing accuracy impact through controlled stages.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes key parameters of the neural network model including pruning ratio, quantization bit-width (e.g., from 32-bit to 8-bit), and activation function parameters. These parameter changes enable model size reduction while optimizing the balance between compression ratio and recognition accuracy.

Inventive Principle:
Principle #35Parameter changes

2Volume of stationary object

If the topology recognition model is compressed, then storage and deployment on IOTIPS terminals becomes feasible, but the computing power requirements change

Engineering Contradiction:
Improvestorage spaceVSAvoidcomputing power
Core Design Contradiction:
Volume of stationary objectVSPower

Solution Approach 1:

The patent replaces high-precision floating-point computations (32-bit/64-bit) with lower-precision fixed-point or integer computations (8-bit/16-bit). This substitution reduces both storage requirements and computational power consumption, making the model suitable for resource-constrained IOTIPS terminals.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the numerical precision parameter from standard floating-point (32-bit) to reduced precision formats (8-bit, 16-bit). This parameter change directly reduces storage volume and computing power requirements while maintaining acceptable recognition accuracy through optimized quantization schemes.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250086460A1Method and apparatus for compressing topology recognition model, electronic device, and medium
Publication Date: 2025.03.13 BEIJING SMARTCHIP MICROELECTRONICS TECHNOLOGY CO LTD
  • US20250086460A1 patent drawing
  • US20250086460A1 patent drawing
  • US20250086460A1 patent drawing

AI summary

Disclosed are a method and apparatus for compressing a topology recognition model, an electronic device, and a medium. The method includes: pruning a to-be-compressed model to obtain a pruned model, and training the pruned model to obtain a trained pruned model; quantifying a bit quantity of a weight parameter of each neural network layer in the trained pruned model from a first bit quantity to a second bit quantity to obtain a highly-quantified pruned model, and training the highly-quantified pruned model to obtain a trained highly-quantified pruned model; using the trained highly-quantified pruned model as the to-be-compressed model, continuously pruning and quantifying the to-be-compressed model until a compressed topology recognition model is obtained, and deploying the compressed topology recognition model on an Internet of Things in Power Systems (IOTIPS) terminal, to reduce a size of the topology recognition model while ensuring the topology recognition model meets an accuracy requirement.