Topside HEMT Cooling With Conductive Passivation and Heat Spreading

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

High electron mobility transistors (HEMTs) operating at high frequencies experience increased heat generation, leading to elevated junction temperatures, which can cause thermal degradation and reduce the reliability and performance of semiconductor devices.

Innovation Solution

Incorporating a thermally conductive passivation layer with a thermal conductivity of at least 80 W/(m·k) between a field plate and a Group III-nitride semiconductor structure, and a heat spreading structure overlapping the gate contact and field plate, to provide additional cooling paths and reduce junction temperatures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If HEMTs operate at high frequencies, then power output and efficiency are improved, but heat generation increases leading to elevated junction temperatures

Engineering Contradiction:
Improvepower outputVSAvoidjunction temperature
Core Design Contradiction:
PowerVSTemperature

Solution Approach 1:

The patent introduces a third-dimensional cooling approach by placing thermally conductive structures on the topside of the semiconductor device, in addition to traditional bottom-side heat sinking. This dimensional expansion allows heat to be extracted from multiple directions simultaneously, enabling high power operation without excessive junction temperature rise.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent employs thermally conductive passivation layers and heat spreading structures as intermediary elements between the heat-generating semiconductor junctions and the external environment. These intermediary structures with high thermal conductivity (≥80 W/(m·k)) efficiently transport heat away from sensitive regions, mediating between the power-generating active region and the heat dissipation pathways.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Power

If high power operation is implemented, then efficiency is improved, but thermal degradation increases reducing reliability

Engineering Contradiction:
Improvepower operationVSAvoiddevice reliability
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

The patent implements preliminary thermal management by pre-positioning thermally conductive passivation layers and heat spreading structures during the fabrication process, before the device operates. This preliminary thermal pathway establishment ensures that heat can be efficiently removed from the outset of high power operation, preventing thermal degradation before it occurs and maintaining reliability throughout the device lifetime.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The implementation of these thermal management strategies effectively lowers junction temperatures, reducing thermal stress, enhancing device reliability, and improving performance by minimizing self-heating effects and increasing power output and efficiency.

Implementation Method 1

The thermally conductive passivation layer may have a thermal conductivity of at least about 80 W/(m·k)

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

The heat spreading structure has a thermal conductivity of at least about 80 W/(m·k)

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS20240429120A1Topside Cooling for Semiconductor Device
Publication Date: 2024.12.26 WOLFSPEED INC
  • US20240429120A1 patent drawing
  • US20240429120A1 patent drawing
  • US20240429120A1 patent drawing

AI summary

Semiconductor devices are provided. In one example, a semiconductor device includes a Group III-nitride semiconductor structure. The semiconductor device may include a gate contact on the Group III-nitride semiconductor structure. The semiconductor device may include a field plate overlapping the Group III-nitride semiconductor structure. The semiconductor device may include a thermally conductive passivation layer overlapping the gate contact. The thermally conductive passivation layer may be between the field plate and the Group III-nitride semiconductor structure. The thermally conductive passivation layer may contact the Group III-nitride semiconductor structure. The thermally conductive passivation layer may have a thermal conductivity of at least about 80 W/(m·k).