Topside Dielectric Plug Layout for Uniform Epitaxial Contacts

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Solution Overview

Problem

The challenge of forming uniform contacts to semiconductor source and drain regions in integrated circuits, particularly in non-planar transistors, is exacerbated by non-uniformity in etching processes due to loading effects, leading to inconsistent contact profiles across the chip.

Innovation Solution

The use of topside dielectric plugs as masking structures with uniform thickness, formed using a sacrificial material to create uniform recesses for conductive contacts, which wrap around the source or drain regions, ensuring consistent contact formation across the integrated circuit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional etching processes are used to form contacts to source and drain regions, then contact formation can be achieved, but loading effects cause non-uniform etching depths and inconsistent contact profiles across the chip

Engineering Contradiction:
Improvecontact profile uniformityVSAvoidloading effects in etching process
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

A dielectric plug is introduced as an intermediary masking structure between the source/drain regions and the etching process. This plug has a different etch rate than the surrounding dielectric material, allowing it to act as a protective barrier during etching. By controlling the plug's dimensions and material properties, uniform contact profiles are achieved across varying distances on the chip, eliminating the harmful loading effects.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If the size of integrated circuits is reduced to continue scaling downward, then device density increases, but contact formation becomes more difficult and non-uniform

Engineering Contradiction:
Improvedevice densityVSAvoidcontact formation uniformity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The dielectric plug is designed with locally optimized dimensions and material properties tailored to each contact region. The plug's height, width, and material composition are adjusted based on the specific requirements of each source/drain region, allowing uniform contact formation even as overall circuit size decreases and device density increases.

Inventive Principle:
Principle #3Local quality

3Adaptability or versatility

If varying distances between source and drain regions are present across the chip, then device layout flexibility is improved, but etching loading effects cause inconsistencies in contact depths

Engineering Contradiction:
Improvedevice layout flexibilityVSAvoidetching depth consistency
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The dielectric plug serves as a mediator that compensates for varying distances between source/drain regions. By positioning the plug at different locations according to the specific geometry of each device, the etching process achieves consistent depths across the entire chip despite layout variations, maintaining both flexibility and precision.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in more uniform epitaxial contact structures, reducing non-uniformity and enhancing ohmic contact quality by using a highly conductive outer layer, such as a silicide layer, thereby improving the electrical performance of the integrated circuit.

Implementation Method 1

selectively etching between adjacent source and drain regions

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS12484281B2Topside plugs for epitaxial contact formation
Publication Date: 2025.11.25 INTEL CORP
  • US12484281B2 patent drawing
  • US12484281B2 patent drawing
  • US12484281B2 patent drawing

AI summary

Techniques are provided herein to form semiconductor devices that use uniform topside dielectric plugs as masking structures to form conductive contacts to various source or drain regions. In an example, a plurality of semiconductor devices each include one or more semiconductor regions extending in a first direction between corresponding source or drain regions. The source or drain regions are adjacent to one another along a second direction different from the first direction. Conductive contacts are formed over the source or drain regions of the semiconductor devices. A dielectric fill is between one or more adjacent pairs of conductive contacts and dielectric masking structures having a substantially uniform thickness are present over the dielectric fill between adjacent pairs of conductive contacts. This uniform thickness characteristic applies to all of the masking structures regardless of their length along the second direction.