Topside Power Delivery Structure for Dense Multi-Die Packages
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Solution Overview
Problem
Communicating large numbers of signals in a multi-die IC package is challenging due to the small size of the dies, design complexities with routing signal and power interconnects, and constraints associated with power delivery.
Innovation Solution
The implementation of a microelectronic assembly with a topside power delivery pathway, utilizing through-substrate vias (TSVs), redistribution layers, and wire bonds to efficiently deliver power to the components, reducing the need for numerous power interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If thousands of power interconnects are used to deliver power to IC components, then power delivery capability is improved, but device complexity and routing complexity increase significantly
Solution Approach 1:
The patent transitions from planar power delivery to three-dimensional power delivery by implementing power pathways on the topside of microelectronic components. Power is delivered through the substrate via TSVs and distributed through redistribution layers on the component's active surface, utilizing the vertical dimension to reduce the number of required interconnects while maintaining adequate power delivery capability
Solution Approach 2:
The substrate and redistribution layers serve multiple functions: they provide mechanical support, enable signal routing, and deliver power distribution. By integrating power delivery functionality into existing structural elements rather than adding dedicated power interconnects, the patent reduces overall device complexity while maintaining power delivery capability
2Power
If numerous power interconnects are implemented, then power delivery is improved, but manufacturing cost and fabrication complexity increase
Solution Approach 1:
The patent combines power delivery pathways with signal routing infrastructure by using the same substrate and redistribution layer structure for both purposes. This merging eliminates the need for separate power interconnect fabrication processes, reducing manufacturing steps and costs while achieving adequate power delivery
Solution Approach 2:
By delivering power through the substrate thickness dimension using TSVs and distributing it on the active surface through redistribution layers, the patent reduces the number of power interconnects required, thereby simplifying the fabrication process and reducing manufacturing costs associated with creating and routing numerous individual power interconnects
3Power
If more power interconnects are used, then power delivery performance is improved, but package size increases
Solution Approach 1:
The patent utilizes the vertical dimension by implementing power pathways through the substrate and distributing power on the component's active surface through redistribution layers. This three-dimensional approach consolidates power delivery into a compact footprint, avoiding the need for additional lateral space that would be required for numerous separate power interconnects
Data Source
AI summary
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a mold material on the package substrate including a first microelectronic component embedded in the mold material, a second microelectronic component embedded in the mold material, and a TMV, between the first and second microelectronic components, the TMV electrically coupled to the first conductive pathway; a redistribution layer (RDL) on the mold material including a second conductive pathway electrically coupled to the TMV; and a third microelectronic component on the RDL and electrically coupled to the second conductive pathway, wherein the second conductive pathway electrically couples the TMV, the first microelectronic component, and the third microelectronic component.


