Topside Power Delivery Structure for Multi-Die Package Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Communicating large numbers of signals in a multi-die IC package is challenging due to the small size of such dies, design complexities with routing signal and power interconnects, and constraints associated with power delivery.
Innovation Solution
The implementation of microelectronic assemblies with topside power delivery structures, including a package substrate with conductive pathways, insulating materials, microelectronic components with through-substrate vias, and redistribution layers to efficiently deliver power to the top surface of components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional power delivery networks are used with multiple power interconnects, then power delivery is achieved, but the number of interconnects increases and package size increases
Solution Approach 1:
The patent transitions from traditional bottom-side power delivery to topside power delivery, utilizing the unused top surface area of the package substrate. This dimensional change allows power interconnects to be routed on the top surface rather than competing for space on the bottom side, reducing the total number of interconnects needed while improving power delivery efficiency
Solution Approach 2:
The power delivery network is segmented into multiple conductive pathways distributed across the top surface of the package substrate. This segmentation allows power to be delivered through multiple parallel paths, reducing the complexity of any single interconnect while maintaining overall power delivery efficiency
2Power
If more power interconnects are added to deliver power to multiple IC components, then power delivery capability is improved, but package size increases
Solution Approach 1:
By moving power interconnect routing to the top surface of the package substrate, the patent utilizes previously underutilized space. This allows multiple power interconnects to be accommodated within the same package footprint without increasing overall package size, while still providing enhanced power delivery capability to multiple IC components
3Adaptability or versatility
If the number of signal and power interconnects is increased, then more IC components can be supported, but routing complexity increases
Solution Approach 1:
The routing complexity is segmented by separating power delivery functions from signal routing functions. Power interconnects are routed through dedicated conductive pathways on the top surface, while signal routing remains on the bottom side. This segmentation allows the package to support more IC components with diverse power and signal requirements without increasing overall routing complexity
Solution Approach 2:
The patent uses the top surface dimension for power interconnect routing, freeing up the bottom side for signal routing. This dimensional separation reduces the complexity of routing both power and signal interconnects simultaneously, allowing the package to accommodate more IC components with cleaner, more manageable routing
Data Source
AI summary
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate, having a surface, including a first conductive pathway electrically coupled to a power source; a first microelectronic component, having an active side electrically coupled to the surface of the package substrate and an opposing back side, surrounded by an insulating material; a second microelectronic component, having an active side electrically coupled to the surface of the package substrate and an opposing back side, surrounded by the insulating material and including a through-substrate via (TSV) electrically coupled to the first conductive pathway; and a redistribution layer (RDL), on the insulating material, including a second conductive pathway electrically coupling the TSV, the second surface of the second microelectronic component, and the second surface of the first microelectronic component.