Torus Interconnect Wiring Management for Data Center Scalability
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Solution Overview
Problem
Current data center and cloud data center network topologies face challenges in scalability, complexity, space utilization, power consumption, and latency due to traditional hierarchical structures, which are not optimized for increased east-west traffic flows and are cumbersome to expand.
Innovation Solution
Implementing a torus or higher radix interconnect structure with a passive patch panel and PCIe cards to simplify wiring and enable efficient routing across a large number of servers, using a multidimensional torus configuration that minimizes hops and allows for flexible expansion without complex cabling or significant structural changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional hierarchical tree structure switches are used, then network connectivity and redundancy are achieved, but device complexity, floor space utilization, and cabling complexity increase significantly
Solution Approach 1:
The network is segmented into multiple torus rings along different dimensions (X, Y, Z axes), where each ring provides independent connectivity paths. This segmentation allows the network to maintain reliability through multiple routing options while reducing cabling complexity compared to a fully connected hierarchical structure.
Solution Approach 2:
The patent transitions from a two-dimensional hierarchical tree structure to a multi-dimensional torus topology (2D, 3D, or higher). By adding dimensional layers, the network achieves enhanced connectivity and redundancy without proportionally increasing cabling complexity, as each node connects to a fixed number of neighbors in each dimension.
2Reliability
If hierarchical tree structure with multiple layers is implemented, then network coverage and redundancy are improved, but deployment complexity and energy costs increase
Solution Approach 1:
The torus topology provides dynamic routing capabilities where packets can be forwarded along multiple dimensional axes to reach destination nodes. This dynamic path selection enables redundancy without requiring static hierarchical layers, simplifying deployment while maintaining reliability through adaptive routing protocols.
3Productivity
If more servers are added to increase processing capacity, then parallel processing capability improves, but network latency and infrastructure complexity increase
Solution Approach 1:
By organizing servers in multi-dimensional torus rings rather than hierarchical layers, the network provides multiple parallel paths for data transmission. This dimensional organization reduces latency for parallel processing workloads by enabling direct routing along dimensional axes rather than requiring traversal through multiple hierarchical levels.
4Reliability
If traditional hierarchical network topology is used, then server connectivity is achieved, but space utilization and scalability are limited
Solution Approach 1:
The patent merges multiple hierarchical layers into a single flattened torus network plane or multi-dimensional equivalent. This consolidation eliminates the need for separate core, aggregation, and edge switch layers, reducing physical space requirements while maintaining server connectivity through the torus routing topology.
Data Source
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AI summary
The present invention provides a method for managing the wiring and growth of a direct interconnect network implemented on torus or higher radix interconnect structure based on an architecture that replaces the Network Interface Card (NIC) with PCIe switching cards housed in the server. Also provided is a passive patch panel for use in the implementation of the interconnect, comprising: a passive backplane that hous4s node to node connectivity for the interconnect; and at least one connector board plugged into the passive backplane comprising multiple connectors. The multiple connectors are capable of receiving an interconnecting plug to maintain the continuity of the torus or higher radix topology when not fully enabled. The PCIe card for use in the implementation of the interconnect comprises: at least 4 electrical or optical ports for the interconnect; a local switch; a processor with RAM and ROM memory; and a PCI interface.