Two-Dimensional Torus PCB Topology for Signal Path Reduction
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Solution Overview
Problem
The two-dimensional torus topology in high-performance computing systems faces signal integrity issues due to long wire lengths between end nodes, leading to increased costs and complexity with adaptations that double connections and layers, and compatibility issues with nodes of varying widths and lengths.
Innovation Solution
A printed circuit board with a two-dimensional torus topology is designed with an array of board connectors, input and output ports, and interconnections, where each connector has identical trace routing directions, and the interconnections form a shortened signal path by not directly connecting the first and last connectors, reducing wire length and maintaining consistent port configurations for compatibility with various electronic modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If long wires are used to connect end nodes in a two-dimensional torus topology, then the topology can be completed to achieve proper interconnection, but signal integrity problems occur due to long trace length
Solution Approach 1:
The patent introduces a dimensional change by routing traces through multiple PCB layers instead of using long single-layer traces. The interconnection traces are distributed across different layers (first layer for horizontal connections, second layer for vertical connections, third layer for wrapping around), effectively reducing the signal path length by utilizing the Z-dimension (layer depth) of the PCB structure.
2Length of stationary object
If adaptations are made to reduce wire length by connecting every other node or bringing nodes to the back, then wire length is reduced, but the number of connections and PCB layers doubles, increasing complexity and cost
Solution Approach 1:
The patent applies local quality by making the trace routing configuration dependent on the specific location of board connectors. Connectors at different positions in the array have different trace routing patterns (some connect horizontally, others vertically, others wrap around), allowing each local region to have optimized trace lengths without requiring a uniform doubling of connections across the entire system.
3Adaptability or versatility
If node configurations are changed to accommodate varying node widths and lengths, then compatibility is improved, but port mapping becomes inconsistent and difficult to manage
Solution Approach 1:
The patent achieves universality by designing board connectors with standardized port configurations that can accommodate different node types and sizes. Each board connector has input ports and output ports arranged in consistent patterns, allowing the same connector design to interface with various electronic modules (compute nodes, storage nodes, network switches) regardless of their specific dimensions or functional characteristics.
Data Source
AI summary
A printed circuit board with a two-dimensional torus topology provided herein. The printed circuit board includes an array of board connectors, an input port and an output port, and a set of interconnections. Each board connector of the array of board connectors is formed to receive an electronic connector. The input port and the output port are formed on each board connector to provide an identical trace routing direction. The set of interconnections are formed to connect each board connector to another board connector. The signal path between each of the interconnections has a length less than a distance between a first board connector and a last board connector in the array of board connectors.