In-Cell Touch Panel Line Resistance Reduction

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The existing capacitive in-cell touch panels face challenges with high resistance in driving lines and sensing lines, particularly in Advanced Super Dimension (ADS) mode, which complicates the manufacturing process and affects the panel's performance.

Innovation Solution

The capacitive in-cell touch panel design incorporates an array substrate with gate lines and data lines, featuring common electrodes and metal wires organized into groups that are electrically connected to form driving and sensing lines, reducing resistance by using metal wires to connect grouped common electrodes and data lines, thereby optimizing the layout for lower resistance and improved performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional discrete driving lines and sensing lines are provided on the touch panel, then touch display function is achieved, but resistance of the lines becomes relatively large

Engineering Contradiction:
Improvetouch display functionVSAvoidline resistance
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent combines driving lines and sensing lines into a unified grid structure where the same transparent electrode patterns serve dual purposes. The first and second transparent electrode patterns form both driving and sensing functions simultaneously, eliminating the need for separate discrete lines and reducing overall resistance.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The transparent electrode patterns are designed to perform multiple functions: they serve as both driving electrodes for liquid crystal control and sensing electrodes for touch detection. This multi-functionality reduces the number of separate conductive paths needed, thereby reducing resistance.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Area of stationary object

If dual gate line structure is employed to increase aperture ratio, then aperture ratio is improved, but manufacturing complexity increases

Engineering Contradiction:
Improveaperture ratioVSAvoidmanufacturing process complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent merges the dual gate line structure with the sensing grid by using the same transparent electrode patterns for both liquid crystal driving and touch sensing. This integration simplifies the manufacturing process while maintaining the high aperture ratio benefits of the dual gate structure.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design effectively reduces the resistance of driving and sensing lines, simplifying the manufacturing process and enhancing the touch panel's performance by allowing for thinner, lighter, and more cost-effective modules with improved aperture ratio and touch sensitivity.

Implementation Method 1

capacitive in-cell touch panel

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

a plurality of gate lines and a plurality of data lines; a plurality of pixels defined by the plurality of gate lines and the plurality of data lines

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentEP2983071B1Embedded capacitive touch screen and display apparatus
Publication Date: 2019.10.09 HEFEI BOE OPTOELECTRONIC TECH CO LTD
  • EP2983071B1 patent drawingFigure 1
  • EP2983071B1 patent drawingFigure 2
  • EP2983071B1 patent drawingFigure 3

AI summary

Embodiments of the invention disclose a capacitive in-cell touch panel and a display device. The touch panel includes an array substrate and a counter substrate, the array substrate includes: pixels defined by gate lines and data lines and a common electrode corresponding to each pixel. All the common electrodes are divided into a plurality of first common electrode groups arranged in a row direction and a plurality of second common electrode groups arranged in a column direction; a plurality of metal wires disposed in a same metal layer, wherein all the metal wires are divided into a plurality of first metal wire groups arranged in the row direction and a plurality of second metal wire groups arranged in the column direction; the first metal wire groups in a direction of a same row are electrically connected to each other, and are electrically connected to first common electrode groups corresponding to them in position, respectively, so as to form a driving line; the second metal wire groups in a direction of a same column are electrically connected to each other, and are electrically connected to second common electrode groups corresponding to them in position, respectively, so as to form a sensing line.