Touch Panel Periphery Traces Multi-Level Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional touch panel manufacturing methods result in thicker devices due to the use of two substrates, which contradicts the trend of thinness in modern computing devices, and existing solutions do not effectively address the thickness and periphery region reduction.
Innovation Solution
The touch panel structure features sensing electrodes directly formed on a cover plate with periphery traces on different levels, connecting same-axis electrodes to narrow the periphery region, and a manufacturing method that includes a color layer, insulating layers, and jumper traces to achieve a thinner design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If sensing assembly is directly laminated on opaque substrate, then manufacturing process is simplified, but touch panel thickness increases
Solution Approach 1:
The patent transitions from a conventional two-substrate laminated structure to a single-substrate structure where sensing electrodes are formed directly on the opaque substrate. This dimensional simplification eliminates the need for a separate sensing substrate, thereby reducing overall touch panel thickness while maintaining manufacturing simplicity.
Solution Approach 2:
The patent extracts and eliminates the sensing substrate from the conventional laminated structure. By forming sensing electrodes directly on the opaque substrate, the design removes the redundant sensing substrate layer, achieving thickness reduction without complicating the manufacturing process.
2Ease of manufacture
If periphery traces are placed on same level, then manufacturing is easier, but periphery region area increases
Solution Approach 1:
The patent utilizes multiple levels (different z-heights) for placing periphery traces. By routing traces at different elevations above the substrate, the design enables tighter spacing and reduced periphery region area while maintaining manufacturing feasibility through standard multi-layer PCB or flexible circuit techniques.
Solution Approach 2:
The patent implements nested routing where periphery traces are arranged in multiple concentric or overlapping layers. This nesting approach allows traces to be packed more efficiently within a smaller periphery area, reducing the overall footprint while maintaining electrical connectivity.
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
A touch panel is provided, comprises a cover plate, a sensor electrode layer, an insulating layer and a jumper layer. The sensor electrode layer is disposed on the cover plate, comprises a plurality of first axis electrodes, a plurality of second axis electrodes, a plurality of bonding pads and a plurality of first periphery traces. Each first axis electrode comprises a plurality of first electrode blocks arranged along a first direction, and the first electrode blocks are electrically connected to each other. Each second axis electrode comprises a plurality of second electrode blocks arranged along a second direction, and the second electrode blocks are electrically isolated from each other. The bonding pads are disposed on the periphery region of the cover plate. The first periphery traces are electrically connected to the bonding pads and the first axis electrodes or the second axis electrodes respectively. An insulating layer is disposed on the sensor electrode layer, wherein a plurality of first via holes and a plurality of second via holes are formed on the insulating layer. Each first via hole exposes the first axis electrodes or the second axis electrodes that are not electrically connected to the first periphery traces, and each second via hole exposes parts of the second electrode blocks of the second axis electrodes. A jumper layer is disposed on the insulating layer. The jumper layer comprises jumper traces and second periphery traces, wherein the second periphery traces are electrically connected to the first axis electrodes or the second axis electrodes through the first via holes, and the jumper traces are electrically connected to the second electrode blocks of the second axis electrodes through the second via holes, wherein the first axis electrodes or the second axis electrodes are not electrically connected to the first periphery traces.