Hardware Accelerator for Touch Sensor Capacitance Processing
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Solution Overview
Problem
Current touch sensors, particularly capacitive touch screens, face challenges in efficiently detecting the presence and location of touches or proximity due to the complexity of processing capacitance changes, which can lead to increased processing time and power consumption.
Innovation Solution
Incorporating a hardware accelerator within the touch-sensor controller that performs operations such as accumulation, multiplication, and tracking maximum/minimum values in parallel, reducing the reliance on general-purpose processors and enhancing the speed of capacitance measurement processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If general-purpose processors are used to process capacitance changes, then processing flexibility is maintained, but processing time and power consumption increase
Solution Approach 1:
The system is divided into two distinct processing segments: a hardware accelerator unit that handles computationally intensive parallel operations (accumulation, multiplication, maximum/minimum tracking), and a microcontroller that manages control logic and lower-complexity tasks. This segmentation allows the hardware accelerator to process capacitance changes at higher speed with optimized power efficiency, while the microcontroller maintains system flexibility.
Solution Approach 2:
A hardware accelerator unit is introduced as an intermediary component between the touch sensor array and the microcontroller. This intermediary performs specialized parallel processing operations that would be computationally expensive for a general-purpose processor, thereby reducing overall processing time and power consumption while maintaining processing flexibility through the microcontroller's continued involvement in control functions.
2Loss of time
If complex capacitance processing operations are performed sequentially, then processing simplicity is maintained, but detection time increases
Solution Approach 1:
The processing operations are segmented into independent parallel tasks: accumulation of capacitance values, multiplication by weights, and tracking of maximum/minimum values. Each segment is handled by dedicated hardware circuits within the accelerator unit, allowing simultaneous execution and dramatically reducing total detection time compared to sequential processing.
Solution Approach 2:
The system transitions from sequential one-dimensional processing to parallel multi-dimensional processing by implementing multiple independent computational pathways within the hardware accelerator. Multiple capacitance samples can be processed simultaneously through different operational pipelines, effectively adding a time-parallelism dimension to the processing architecture.
Data Source
AI summary
In one embodiment, a method comprises detecting, by a hardware accelerator, that a value has been written to a first location of a memory, the first location identified by a first address. The method further includes adding the value to an accumulated value stored in an accumulator register of the hardware accelerator and storing the result in the accumulator register. The method further includes comparing the value to a maximum value stored in a first register of the hardware accelerator and overwriting the maximum value with the value if the value is greater than the maximum value. The method also includes comparing the value to a minimum value stored in a second register of the hardware accelerator and overwriting the minimum value with the value if the value is less than the minimum value.