Thermal Pyrolytic Graphite Shadow Ring for Plasma Chamber Heat Dissipation
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Solution Overview
Problem
Conventional wafer dicing methods such as scribing and sawing result in chipping, cracking, and waste of wafer real estate due to jagged separation lines and the need for excessive spacing between dies, while plasma dicing faces cost and throughput limitations, especially with metals like copper.
Innovation Solution
A hybrid method combining femtosecond-based laser scribing and plasma etching using a TPG shadow ring or plasma thermal shield for heat dissipation and shielding, allowing for precise and efficient separation of integrated circuits without thermal damage and reducing the need for lithography patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional scribing or sawing is used for wafer dicing, then the separation of individual dies is achieved, but chipping and cracking occur along the severed edges and cracks can propagate into the substrate rendering integrated circuits inoperative
Solution Approach 1:
The patent replaces mechanical scribing and sawing systems with a plasma-based dicing system. The plasma process uses reactive ion etching to separate dies without mechanical contact, eliminating the chipping and cracking problems inherent in mechanical methods. The plasma selectively etches the street regions between dies through a patterned mask, achieving clean separations that preserve integrated circuit integrity.
Solution Approach 2:
The patent changes the physical and chemical parameters of the dicing process by using plasma chemistry instead of mechanical force. By controlling plasma power, gas composition, and pressure parameters, the process achieves precise etching of street regions while protecting the die regions. The patterned mask controls plasma exposure to ensure selective removal of material only in the street areas.
2Productivity
If conventional scribing or sawing is used for wafer dicing, then separation of dies is achieved, but excessive spacing must be maintained between dies to prevent damage, resulting in waste of wafer real estate
Solution Approach 1:
The plasma-based dicing system enables tighter spacing between dies because it does not generate the mechanical stresses and debris that cause chipping and cracking. The reactive ion etching process cleanly separates dies at the precise mask boundaries without requiring additional safety margins, thereby maximizing the usable wafer area and increasing die density.
3Productivity
If sawing is used for wafer dicing, then thick wafers can be separated, but the blade thickness and required spacing result in significant waste of wafer real estate
Solution Approach 1:
The plasma dicing process replaces the physical saw blade with a field-based etching mechanism. This eliminates the blade thickness constraint entirely, allowing separation of thick wafers with minimal kerf width. The plasma etches through the entire wafer thickness vertically through the street regions, achieving clean separation without the lateral material removal required by mechanical sawing.
4Productivity
If plasma dicing is implemented, then cost and throughput limitations are reduced, but additional processing steps and equipment complexity are introduced
Solution Approach 1:
The plasma processing equipment used for dicing can also perform other semiconductor fabrication functions such as surface preparation, pattern transfer, and material removal in various process stages. This multi-functionality justifies the equipment investment by utilizing the same plasma reactor for multiple operations, thereby reducing overall facility complexity and cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables clean separation of integrated circuits with minimal thermal damage, allowing for denser packing and increased wafer efficiency by reducing chipping and cracking, and lowering costs through reduced need for lithography and improved throughput.
Implementation Method 1
Each of the plurality of posts includes an inner core of thermal pyrolytic graphite (TPG)
Implementation Method 2
plasma etching through the streets to singulate the integrated circuits
Implementation Method 3
femtosecond-based laser scribing
Data Source
AI summary
Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a shadow ring assembly for a plasma processing chamber includes an annular body including a thermally conductive material. The annular body includes a top surface to face an interior of the plasma chamber, and a bottom surface to face a substrate carrier in the plasma chamber. A plurality of posts are attached to the annular body and positioned substantially below the bottom surface of the annular body. Each of the plurality of posts includes an inner core of thermal pyrolytic graphite (TPG). The shadow ring assembly also includes a plasma resistant coating on the annular body and the plurality of posts.