TPM Register Virtualization With Buffered Command Transfer
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Solution Overview
Problem
The high hardware costs associated with implementing a TPM module for communication with a host are a result of the TPM register being implemented solely in hardware, requiring a large chip area.
Innovation Solution
Implementing the TPM register through software simulation using a divided memory space and introducing a receive and transmit buffer, reducing the hardware requirements by allowing the buffers to store only a portion of the command data, thereby minimizing the chip area needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the TPM register is implemented by hardware only, then the TPM can store complete TPM command data, but the chip area and hardware costs increase significantly
Solution Approach 1:
The patent segments the data storage function into two parts: the hardware receive buffer for initial data reception and the software-simulated TPM register in memory for complete command data storage. This segmentation allows the hardware portion to be minimal while the software portion handles the bulk of data storage requirements
Solution Approach 2:
The patent introduces a software layer (driver) as an intermediary between the hardware receive buffer and the logical TPM register. This software mediator manages the data transfer and simulation, allowing the hardware to remain simple while providing full TPM register functionality through software
2Ease of manufacture
If the receive buffer stores only payload data, then hardware costs are reduced, but the buffer size must be precisely controlled
Solution Approach 1:
The patent implements feedback mechanisms where the TPM logic module monitors the receive buffer status and triggers processor intervention when the buffer reaches threshold levels. This feedback loop automates buffer management, reducing the complexity burden on manual configuration while maintaining cost-effective hardware design
3Area of stationary object
If the TPM register is software-simulated, then chip area is reduced, but data transfer latency must be minimized
Solution Approach 1:
The patent performs preliminary actions by having the processor dump receive buffer data into the TPM register in advance, before the host needs to access it. This proactive data preparation reduces latency when the host requests TPM command data, as the software-simulated register is already populated and ready for immediate access
Data Source
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AI summary
The present disclosure provides a communication method of a TPM, a TPM, a board, and a device, and is applied to the field of computer technologies. The TPM includes a TPM logic module, a receive buffer, a TPM register, and a processor. The TPM register is a storage space obtained by dividing a memory of the TPM. The TPM logic module receives a TPM register write command sent by a host, and stores a payload of the write command into the receive buffer. The payload of the TPM register write command is a part or all of content forming TPM command data. When data in the receive buffer reaches a first data amount threshold, the processor dumps the data in the receive buffer into the TPM register. When all the content of the TPM command data is stored in the TPM register, the processor executes the TPM command data. This can resolve a problem of high TPM hardware costs due to use of a hardware-only solution for TPM communication in related technologies.