TPT Violation Detection via Color Graph Visualization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional design rule checker (DRC) tools cannot detect triple patterning technology (TPT) spacing violations, which are distinct from double patterning technology (DPT) odd loop violations, posing a challenge in manufacturing integrated circuits with complex design rules and multiple masking technologies.
Innovation Solution
A method and system for TPT violation detection and visualization that maps design layout violations to a graph, generates a color graph, detects TPT violations, and visualizes them on a layout canvas, utilizing a graph generator module, detector module, and visualizer module to identify and highlight spacing violations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DRC tools are used for layout verification, then DPT odd loop violations can be detected, but TPT spacing violations cannot be detected
Solution Approach 1:
The violation detection process is segmented into distinct modules: a graph generator module that creates conflict graphs from layout violations, a detector module that analyzes the color graph for TPT violations, and a visualizer module that displays results. This segmentation allows the system to handle different masking technologies (DPT and TPT) through specialized detection algorithms while maintaining a unified architecture.
Solution Approach 2:
The DRC tool is designed with multi-functionality to detect both DPT odd loop violations and TPT spacing violations using a unified graph-based approach. The system generates color graphs that can represent different types of violations and applies appropriate detection algorithms based on the masking technology being used, making the tool adaptable to multiple manufacturing processes.
2Measurement precision
If TPT violation detection is implemented, then detection accuracy for TPT spacing violations improves, but system complexity increases
Solution Approach 1:
A color graph serves as an intermediary data structure between the layout input and violation detection output. The graph generator module converts layout geometry and design rules into a color graph representation where nodes represent shapes and edges represent spacing constraints. This intermediary representation simplifies the detection process by transforming complex geometric relationships into graph coloring problems that can be solved algorithmically.
Solution Approach 2:
The patent replaces traditional geometric-based violation detection mechanisms with a graph-theory-based approach. Instead of directly analyzing spatial relationships and distances in the layout, the system substitutes this with graph generation and coloring algorithms, which are more systematic and easier to implement for TPT spacing violation detection.
Data Source
AI summary
A method, system, and computer program product for triple patterning technology (TPT) violation detection and visualization within an integrated circuit design layout are disclosed. In a first aspect, the method comprises mapping a plurality of violations of the integrated circuit design layout to a graph, generating a color graph corresponding to the graph, detecting at least one TPT violation from the color graph; and visualizing the at least one TPT violation on a layout canvas. In a second aspect, the system comprises a graph generator module for mapping a plurality of violations of the integrated circuit design layout to a graph and to generate a color graph corresponding to the graph, a detector module for detecting at least one TPT violation from the color graph, and a visualizer module for visualizing the at least one TPT violation on a layout canvas.