Trace-Based Coherent Cache Memory Traffic Generator
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Solution Overview
Problem
Existing processor core performance simulators struggle to accurately model memory traffic and heterogeneous processor performance due to their reliance on synthetic memory access patterns and limited core modeling capabilities.
Innovation Solution
A trace-based coherent cache driven memory traffic generator is used in a core simulator to model actual memory traffic by receiving workload traces and simulating data exchanges with a shared memory subsystem, excluding core elements irrelevant to system-level performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If synthetic memory access patterns are used to model memory traffic, then the simulation can be performed with limited core modeling, but the representativeness of memory traffic modeling deteriorates
Solution Approach 1:
The patent uses workload traces (actual recorded memory access patterns from real processors) to copy realistic memory traffic behavior into the simulation environment. Instead of generating synthetic patterns, the system imports actual trace data that captures genuine memory access characteristics, thereby improving representativeness without requiring complex core modeling.
2Measurement precision
If full core elements are modeled in the simulator, then measurement precision improves, but computation intensity increases
Solution Approach 1:
The patent extracts only the essential components needed for memory traffic simulation (memory subsystem, cache hierarchy, interconnect) while excluding irrelevant core elements (instruction decoding, execution units, register files). This extraction allows accurate memory subsystem performance measurement without the computational overhead of modeling complete processor cores.
Solution Approach 2:
The simulation system is segmented into independent functional modules: workload trace processor, memory traffic generator, memory subsystem model, and performance analyzer. This segmentation allows each module to be optimized independently and enables parallel processing of multiple workload traces, reducing overall computation intensity.
3Productivity
If multiple workload traces are processed simultaneously, then productivity improves, but device complexity increases
Solution Approach 1:
The traffic generator is designed as a universal module that can process multiple different workload trace formats simultaneously. It implements a standardized interface that accepts various trace types (instruction traces, data traces, mixed traces) and generates corresponding memory traffic patterns, enabling multi-functional operation without proportionally increasing complexity.
Data Source
AI summary
A core simulator includes one or more simulated processors, a trace-based traffic generator, and a simulated memory subsystem. Each simulated processor includes a core element and at least one lower-level cache excluded from the core element. The trace-based traffic generator includes a plurality of modeled caches that model the at least lower-level cache without modeling the core element. The trace-based traffic generator is configured to receive at least one workload trace and based on the workload trace simulate actual memory traffic to be processed by the simulated memory subsystem. The simulated memory subsystem is shared between the at least one simulated processor and the trace-based traffic generator. The trace-based traffic generator performs a data exchange with the memory subsystem based on the at least one workload trace. The data exchange impacts a measured performance of the at least one simulated processor.