Trace Buffer CPU Halt Mechanism for Debugging Limited Pin Processors
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Solution Overview
Problem
Low-end data processor devices face challenges in determining trace information due to limited pins for the debug interface, limiting their ability to notify and provide trace information to external devices.
Innovation Solution
A data processor device with a trace buffer that stores trace information, including program profiling and dynamic program trace information, and operates in either a lossless mode where the CPU is halted when the buffer is full or a lossy mode where new information overwrites old, allowing continuous execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If a trace buffer is implemented to store trace information, then trace information storage capability is improved, but device complexity increases due to additional buffer management hardware
Solution Approach 1:
The trace buffer operates autonomously by automatically detecting when it is full and generating halt signals to the CPU without requiring external intervention. The buffer self-manages its contents by overwriting old trace data when full, eliminating the need for complex external buffer management hardware or software.
Solution Approach 2:
The system changes the operational state parameter of the CPU by generating halt signals based on trace buffer fullness. This parameter change (CPU halt/resume) simplifies buffer management by using the CPU's own execution state control rather than requiring separate buffer management hardware.
2Reliability
If the CPU is halted when the trace buffer is full to prevent data loss, then trace information完整性 is improved, but productivity decreases due to execution pauses
Solution Approach 1:
The system applies partial action by halting the CPU only temporarily and selectively when the trace buffer reaches capacity, rather than continuously halting or using complex data loss prevention mechanisms. This partial halt approach ensures trace data integrity while minimizing productivity impact compared to continuous execution pauses.
Solution Approach 2:
When the trace buffer is full, the system discards old trace data by overwriting it with new trace information, similar to circular buffer behavior. This discarding mechanism maintains trace data integrity for the most recent executions while allowing the CPU to resume quickly without prolonged halts, thus balancing reliability and productivity.
3Loss of information
If trace information is stored continuously without mode selection, then trace data completeness is improved, but device complexity increases due to additional control mechanisms
Solution Approach 1:
The trace buffer operates dynamically by automatically switching between two operational modes based on buffer fullness: normal mode for data collection and overwrite mode when full. This dynamic behavior eliminates the need for complex external mode control mechanisms while ensuring trace data completeness through automatic adaptation.
Solution Approach 2:
The trace buffer self-determines its operational mode by monitoring its own fullness state and automatically generating appropriate responses (halt signals or overwrite operations). This self-service capability provides complete trace data collection without requiring additional external control hardware or complex mode management mechanisms.
Data Source
AI summary
In response to determining an event has occurred, information is stored at a trace buffer of an integrated circuit. When the trace buffer is full, execution of instructions at a CPU is halted to allow the trace buffer information to be accessed at an external interface to the integrated circuit device. The CPU is continually halted as the trace buffer is filled to facilitate retrieving all information written to the trace buffer.