Trace Circuit Reference Address Register Compression
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Solution Overview
Problem
Existing data processing systems face challenges in efficiently compressing trace data streams, leading to potential overflow or bandwidth exceeding issues due to the inclusion of unnecessary address information, especially when memory addresses are similar across processing operations.
Innovation Solution
A data processing apparatus with a trace circuitry that utilizes multiple reference address registers to select the most efficient register for each memory address, generating trace data elements that indicate the selected register and the difference between the memory address and the selected reference address, thereby reducing the amount of data required for trace compression.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single reference address register is used to store reference addresses for trace compression, then the device complexity is reduced, but the trace data compression efficiency deteriorates when multiple types of instructions with different address patterns are processed
Solution Approach 1:
The trace unit employs multiple reference address registers (first reference address register for instruction addresses, second reference address register for load/store addresses) that can be selectively activated based on the instruction type being processed. This multi-functional approach allows each register to specialize in compressing addresses for specific instruction categories, thereby improving overall compression efficiency without significantly increasing device complexity.
Solution Approach 2:
The trace unit dynamically selects which reference address register to use based on the type of instruction being executed. The selection logic adapts the reference address storage mechanism to match the current processing context, allowing optimal compression for each instruction type while maintaining a relatively simple fixed structure for the registers themselves.
2Measurement precision
If all bits of the memory address are included in the trace data stream, then the measurement precision of address tracking is improved, but the quantity of trace data increases leading to buffer overflow or bandwidth exceeding
Solution Approach 1:
The trace unit extracts and transmits only the necessary portion of the memory address in the trace data stream. By comparing the full memory address with the reference address stored in the selected register, the unit identifies and transmits only the differing bits (or offset), thereby maintaining complete address tracking capability while significantly reducing the volume of trace data that must be stored and transmitted.
Solution Approach 2:
The trace data transmission employs variable encoding where the number of bits transmitted depends on the local characteristics of each address. When the memory address closely matches the reference address, fewer bits are transmitted; when differences are larger, more bits are transmitted. This local adaptation of data quality ensures precise address tracking is maintained wherever needed while minimizing data volume where possible.
Data Source
AI summary
A trace circuit 8 is configured to generate a stream of trace data elements indicative of processing operations performed by a processing circuit 4. The trace circuit 8 has a plurality of reference address registers 30-1 configured to store corresponding reference addresses. When the processing circuit 4 performs a processing operation associated with an associated memory address, the trace circuit 8 selects one of the reference address registers 30-1 as a selected reference address register, and generates a trace data element indicating: (i) which of the reference address registers 30-1 is the selected reference address register, and (ii) a difference, if any, between the associated memory address and the reference address of the selected reference address register. A diagnostic apparatus 20 for analyzing the trace stream has a similar set of reference address registers 30-2 which are used to reconstruct the associated memory address from the generated trace data element.