Trace Compaction Circuit for Emulation Processor Clusters
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Solution Overview
Problem
Existing hardware functional verification systems face inefficiencies in capturing trace data during emulation of integrated circuit designs, as they often require dedicated resources and result in wasted trace capacity due to the need to capture all outputs simultaneously, limiting targeted recording and extending emulation steps.
Innovation Solution
A method and system for compacting trace data generated by emulation processors, involving the generation of data bits, association with enable bits, selection of trace data bits, and accumulation into state elements, with a hardware functional verification system utilizing trace compaction circuits and registers to efficiently store and output trace data bytes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated trace output connections are used for all emulation processor outputs, then complete trace data capture is achieved, but trace capacity is wasted and emulation steps are extended
Solution Approach 1:
The patent extracts only the necessary trace data bits from the full set of emulation processor outputs by using enable bits to identify which outputs should be captured. This selective extraction eliminates the waste of trace capacity on non-essential data while maintaining complete capture of relevant trace information.
Solution Approach 2:
Instead of capturing all emulation processor outputs uniformly, the patent applies partial action by capturing only the subset of outputs that are marked with enable bits. This partial capture approach optimizes trace capacity utilization while still achieving complete capture of the necessary trace data for verification purposes.
2Reliability
If all emulation processor outputs are captured simultaneously, then comprehensive trace data is obtained, but dedicated resources are required and emulation performance is limited
Solution Approach 1:
The patent makes the trace capture system universal by using a single shared trace output connection that can capture data from any emulation processor output that is marked with an enable bit. This eliminates the need for dedicated trace output connections for each processor while maintaining the ability to capture comprehensive trace data selectively.
Solution Approach 2:
The trace capture system becomes dynamic through the use of enable bits that can be configured to select different subsets of processor outputs at different times. This dynamic selection capability allows the system to adapt to different verification needs without requiring physical reconfiguration of dedicated trace connections, thereby reducing device complexity.
3Device complexity
If a single capture control signal is used for all trace outputs, then simple control logic is achieved, but targeted recording of specific trace outputs is prevented
Solution Approach 1:
The patent applies preliminary action by pre-marking the desired trace outputs with enable bits before the actual trace capture process begins. This preliminary marking allows the simple capture control signal to selectively capture targeted outputs without requiring complex control logic, as the selection criteria are established in advance through the enable bit configuration.
Data Source
AI summary
The present patent document relates to a method to compact trace data generated by emulation processors during emulation of a circuit design, and a hardware functional verification system that compacts trace data. Compaction logic within emulation processor clusters accumulated data bits output from the emulation processors and compacts them into trace data bytes in registers based on enable bits identifying valid trace data according to a compaction scheme. Trace data bytes are further accumulated and compacted into larger trace data bytes in higher level processor clusters of the emulation chip according to a compaction hierarchy, with the compacted trace data bytes stored into a trace array of the emulation chip.