Trace Data Offload Architecture for Integrated Circuit Tile Analysis
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Solution Overview
Problem
Modern integrated circuits face challenges in handling and analyzing trace data from data processing arrays due to the high volume and complexity of the data, requiring efficient offload and storage solutions.
Innovation Solution
A trace data offload architecture is implemented in the design of a data processing array within an integrated circuit, allowing for the configuration of selected tiles to generate trace data based on user-specified settings, and conveying this data to a memory using the offload architecture for further analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If trace data is collected from data processing array, then debugging capability is improved, but bandwidth and storage requirements increase significantly
Solution Approach 1:
The patent extracts only the necessary trace data from the data processing array by allowing selective enabling of trace functionality in specific tiles. The trace data is then offloaded to external memory rather than being stored entirely on-chip, effectively removing the burden of storing large volumes of trace data within the IC while maintaining debugging capability.
Solution Approach 2:
The data processing array is divided into multiple tiles, and trace functionality can be selectively enabled in specific tiles based on debugging needs. This segmentation allows trace data to be collected only from relevant portions of the array, reducing the total volume of trace data while maintaining effective debugging capability.
2Reliability
If trace functionality is added to data processing array, then design verification is improved, but device complexity increases
Solution Approach 1:
The trace data offload architecture uses existing multi-functional components within the data processing array, such as the tile interconnect and memory interfaces, to convey trace data. By reusing existing infrastructure for multiple purposes (data processing and trace data offload), the patent avoids adding significant architectural complexity while maintaining design verification capability.
3Quantity of substance
If on-chip storage is increased to handle trace data, then trace data capacity is improved, but area and cost increase
Solution Approach 1:
The patent introduces external memory as an intermediary storage location for trace data. Instead of expanding on-chip storage, the trace data is conveyed through the trace data offload architecture to external memory, which serves as a mediator between the data processing array and the trace data storage requirements, eliminating the need for large on-chip storage area.
Data Source
AI summary
Event trace includes implementing a design for a data processing array of a target integrated circuit (IC) by, at least in part, adding a trace data offload architecture to the design. One or more selected tiles of the data processing array used by the design as implemented in the target IC are configured to generate trace data based on user-specified runtime settings for performing a trace. During execution of the design by the data processing array, trace data as generated by the one or more selected tiles of the data processing array is conveyed to a memory of the target IC using the trace data offload architecture. A trace report is generated from the trace data using a data processing system coupled to the target IC.