On-Chip Trace Engine Selective Data Reduction for Overflow
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Solution Overview
Problem
Current on-chip trace architectures face limitations due to constrained memory and I/O resources, leading to a limited sampling window and potential corruption of the device under test when recording trace data, with existing solutions either discarding data or relying on lossy compression methods.
Innovation Solution
An on-chip trace engine that selectively engages data reduction mechanisms, such as data width reduction, pattern match elimination, and under-sampling, to manage overflow conditions and stream high-frequency trace data losslessly through chip output pins to external capture devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If trace data is stored in on-chip arrays, then trace capture capability is provided, but the sampling window is limited due to constrained memory resources
Solution Approach 1:
The patent transitions from purely on-chip storage to a hybrid architecture that adds an external storage dimension. Trace data is captured on-chip and then streamed off-chip to external memory, effectively expanding the storage capacity beyond the physical constraints of the chip while maintaining the capture capability.
Solution Approach 2:
The patent introduces an intermediary streaming mechanism that bridges the on-chip trace capture unit and off-chip storage. This intermediary component enables data to be transferred from the constrained on-chip environment to the unconstrained external environment, resolving the storage capacity limitation.
2Quantity of substance
If main memory is used for trace data storage, then storage capacity is significantly larger, but the processor must be stalled or trace engine must steal bus cycles which corrupts the device under test
Solution Approach 1:
The patent extracts the trace data storage function from the on-chip environment and places it in external memory. This separation allows the trace engine to write data continuously without needing to stall the processor or steal bus cycles, as the external memory does not share the same data path resources as the processor.
Solution Approach 2:
The patent segments the trace system into distinct functional components: an on-chip trace capture unit and an off-chip storage unit. This segmentation allows each component to operate independently without interfering with the other, enabling continuous trace capture without disrupting processor operation.
3Speed
If chip output pins are used to stream trace data, then data can be captured at high frequency, but data rate must be reduced through discarding samples or encoding which loses information
Solution Approach 1:
The patent uses chip output pins not for direct high-speed data output but as a control dimension to enable or disable data reduction mechanisms. This allows the system to maintain high-frequency capture by switching between different data reduction strategies based on the pin state, preserving information that would otherwise be lost.
Solution Approach 2:
The patent implements dynamic data reduction mechanisms that can be selectively engaged or disengaged based on overflow conditions. This dynamic approach allows the system to adapt the data reduction level in real-time, maintaining information completeness when possible while still providing a pathway for high-frequency data capture.
4Quantity of substance
If data reduction mechanisms are engaged to expand trace capture window, then more data can be stored, but compressibility limits the array capacity expansion
Solution Approach 1:
The patent introduces an intermediary overflow detection and management mechanism that sits between the trace capture unit and the storage system. This intermediary monitors data volume and selectively engages data reduction mechanisms only when needed, rather than applying compression continuously. This resolves the contradiction by making data reduction adaptive rather than dependent on data compressibility characteristics.
Solution Approach 2:
The patent changes the operational parameters of the data reduction mechanisms based on overflow conditions rather than applying fixed compression. When overflow is detected, the system engages data reduction; when no overflow exists, it operates without reduction. This parameter-based control allows the system to expand capture volume without being limited by data compressibility.
Data Source
AI summary
An on-chip trace engine stores trace data in on-chip trace arrays and routes the trace data to output pins. An external trace capture device captures the trace data. The on-chip trace engine streams the trace data through the debug output pins at a slower rate that can be supported by external trace capture device. If compression is insufficient for the required data rate reduction, the on-chip trace engine includes selectable data reduction mechanisms. Responsive to an overflow condition, meaning trace data is captured in on-chip trace arrays faster than it can be routed off chip, the on-chip trace engine enters an overflow mode in which one or more of the data reduction mechanisms are selected. The data reduction mechanisms may include, for example, a data width reduction component, a pattern match data elimination component, a priority source select component, an under-sampling component, or various combinations thereof.