Trace Generation Logic for Data Processing Apparatus
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Solution Overview
Problem
The finite bus bandwidth and trace buffer size in data processing systems limit the volume of trace elements that can be generated and analyzed, particularly for complex processor cores, leading to inefficiencies in tracing and increased data volume with cycle accurate mode operations.
Innovation Solution
Implementing trace generation logic that generates trace timing indicators for predetermined pluralities of clock cycles, reducing the volume of trace data while maintaining sufficient cycle accuracy, and allowing configurable processing timing intervals to adapt to different tracing needs and available bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If cycle accurate mode operation is used to trace processor activities, then measurement precision is improved, but the volume of trace data increases significantly
Solution Approach 1:
The patent changes the parameter of time measurement from single clock cycle resolution to multi-clock cycle intervals. The trace timing indicator specifies intervals of multiple clock cycles rather than tracing every individual cycle, thereby reducing trace data volume while maintaining sufficient measurement precision for debugging and analysis purposes.
2Loss of information
If trace buffering is implemented to store trace elements, then information retention is improved, but the finite buffer size and bus bandwidth limit the volume of trace elements that can be generated
Solution Approach 1:
The patent reduces the parameter of trace data generation rate by using multi-clock cycle timing intervals. This allows the finite buffer to accommodate larger volumes of trace elements over extended periods, effectively increasing the total trace element volume that can be captured without expanding buffer size or bus bandwidth.
3Measurement precision
If instruction and data value tracing are performed simultaneously to correlate activities, then measurement completeness is improved, but the bit rate and trace data volume increase
Solution Approach 1:
The patent applies multi-clock cycle timing intervals to both instruction tracing and data value tracing operations. By synchronizing both trace types to the same extended time intervals, the system maintains the ability to correlate instruction execution with data access patterns while reducing the overall bit rate by eliminating redundant single-cycle timing information.
Data Source
AI summary
A data processing apparatus and method are provided for generating a trace stream. The data processing apparatus comprises logic for producing data elements, and trace logic for producing a stream of trace elements representative of at least some of the data elements. The trace logic has trace generation logic operable to generate trace elements for inclusion in the stream, and is further arranged to generate trace timing indicators for inclusion in the stream. Each trace timing indicator indicates the elapse of one or more processing timing intervals, the processing timing interval being a predetermined plurality of clock cycles.