Trace Logic Partitioning for Cycle-Accurate Emulation
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Solution Overview
Problem
Current processor and memory emulation technologies face challenges in accurately modeling cache-based architectures, leading to performance discrepancies and a lack of visibility into system behavior, which hinders debugging and profiling, especially with the introduction of cache-based systems and multiple CPU cores.
Innovation Solution
The solution involves cycle-accurate simulation by partitioning trace logic to free-run while functional logic is stepped, allowing for the export of trace information at a slower clock rate to capture system states, along with data compression and adaptive calibration techniques to improve data extraction and recording accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If simulation is used to model cache-based architectures, then development time is reduced, but performance accuracy deteriorates (simulated performance can be 50-100% away from actual target performance)
Solution Approach 1:
The system is divided into two distinct components: a simulator for rapid development and an emulator for accurate measurement. The simulator handles early development stages where speed is critical, while the emulator takes over for performance-critical stages where accuracy is paramount. This segmentation allows developers to benefit from both fast simulation and accurate emulation without compromise.
Solution Approach 2:
The patent introduces cycle-accurate trace information as an intermediary between the simulator and emulator. This trace data captures actual system behavior and serves as a bridge, allowing the emulator to provide precise performance measurements while the simulator continues to enable rapid development. The trace information mediates between the two systems to ensure consistency.
2Measurement precision
If emulators are introduced to provide visibility into system behavior, then measurement accuracy is improved, but device complexity increases
Solution Approach 1:
The patent creates a cycle-accurate copy of the target system's behavior through tracing. Instead of directly emulating the entire complex cache-based architecture, the system traces and records the actual execution cycles and events, then uses this trace data to provide visibility into system behavior. This copying approach simplifies the measurement system while maintaining accuracy.
3Measurement precision
If cycle-accurate tracing is implemented, then performance measurement accuracy is improved, but data processing complexity increases
Solution Approach 1:
The patent extracts only the essential cycle-accurate trace information needed for performance measurement from the complex system behavior. By selectively capturing and exporting only the relevant timing and event data, the system achieves accurate performance measurement without the need to process and analyze all system details, thereby reducing data processing complexity.
Data Source
AI summary
The trace logic are separate from the clocks that operate the system logic. This allows the chip to be placed in a special mode where the functional logic is issued one clock. One frame of trace data is generated for each functional clock issued. A valid signal may be implemented changing state when new information is generated. The trace logic, whose clock is free running, detects the change in state in the valid signal. It then processes the trace information presented to it, exporting this information to a trace recorder. When transmission of this information has created sufficient space to accept a new frame of trace information, the empty signal is generated. This causes the clock generation logic to issue another clock to the system logic.