Trace Logic for Shared Buffer Monitoring in SoCs
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Solution Overview
Problem
Existing hardware trace modules in SoCs are limited in tracing data buffer contents, especially for shared buffers, as they only generate trace messages on read/write accesses by the core element, failing to accurately monitor content changes made by other system elements, and provide incomplete data representation, complicating debugging and requiring additional hardware modules.
Innovation Solution
The integrated circuit incorporates trace logic that detects triggers on program flow and data accesses, performs direct memory access to shared buffers, and generates memory content messages, providing comprehensive trace information without additional hardware modules, enabling accurate observation of shared buffer contents and flexible data representation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple hardware trace modules are added to monitor shared buffers, then measurement precision improves, but device complexity increases
Solution Approach 1:
The trace module is enhanced with DMA capability that enables it to monitor shared buffers independently of core accesses. The same trace module can now serve multiple functions: tracking core accesses via virtual bus and independently monitoring shared buffer contents through DMA, eliminating the need for separate monitoring modules.
Solution Approach 2:
The DMA controller acts as an intermediary that enables the trace module to access shared buffers directly without going through the core element. This intermediary mechanism allows the trace module to capture buffer content changes made by any system element, not just the core, thereby improving trace accuracy without adding multiple modules.
2Loss of information
If trace messages include complete buffer content, then loss of information decreases, but use of energy increases
Solution Approach 1:
Instead of continuously transmitting complete buffer contents, the system uses partial action by only capturing and transmitting buffer content when specific trigger events occur (core reads/writes or DMA accesses). This selective approach provides sufficient debugging information while minimizing energy consumption compared to continuous full-buffer monitoring.
Solution Approach 2:
The buffer content is captured in advance and stored in the trace buffer when trigger events occur, rather than continuously monitoring and transmitting. This preliminary capture approach ensures complete data is available when needed for debugging while avoiding the continuous energy expenditure of real-time transmission.
3Loss of information
If trace buffer size increases, then loss of information decreases, but area of stationary object increases
Solution Approach 1:
The trace buffer is designed to store only the necessary trigger information and associated buffer contents rather than continuously logging all system activity. This partial logging approach captures sufficient debugging information while keeping the buffer size manageable and minimizing the area required for the trace buffer.
Data Source
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AI summary
An integrated circuit comprises trace logic (310) for operably coupling to at least one memory element (360) and for providing trace information for a signal processing system (300). The trace logic (310) comprises trigger detection logic (410) for detecting at least one trace trigger (405), memory access logic (420) arranged to perform, upon detection of the at least one trace trigger (405), at least one read operation (425) for at least one memory location (380) of the at least one memory element (360) associated with the at least one detected trigger (405), memory content message generation logic (430) arranged to generate at least one memory content message (435) comprising information relating to a result of the at least one read operation performed by the memory access logic (420), and output logic (440) for outputting (445) the at least one memory content message.