Trace Processor Control for Multi-Core Bandwidth-Limited Data Capture
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Solution Overview
Problem
In modern processor architectures with integrated cores, caches, and memories, traditional bus trace methods are ineffective due to the lack of external memory interfaces, leading to challenges in recording program flow and data access operations, especially in multi-core systems where high bandwidth requirements are intensified.
Innovation Solution
A control system comprising a central processor and a trace processor communicatively coupled via an inter-processor bus, where the central processor writes data to an operations memory, and the trace processor filters and transmits trace data through a trace port, using processor address registers associated with predetermined operations to manage data transmission and processing, thereby overcoming bandwidth limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional bus trace methods are used to record memory access operations, then program flow and data access can be determined, but the method becomes ineffective in systems with integrated caches and memories that lack external memory interfaces
Solution Approach 1:
The patent introduces a trace interface as an intermediary component between the processor core and the external trace tool. This trace interface includes a trace buffer and trace logic that intercepts and records memory access operations before they reach the external bus, enabling tracing in systems without external memory interfaces. The trace interface acts as a mediator that captures the necessary information internally and makes it available to external debugging equipment.
Solution Approach 2:
The patent transitions from external bus-based tracing to internal trace interface-based recording by adding a new dimension of observation. Instead of relying solely on external bus signals, the system incorporates an internal trace port that provides direct access to memory access information within the processor, effectively creating a new channel for data capture that bypasses the limitations of external interfaces.
2Speed
If high-speed serial interfaces with differential low-voltage swing signalling are used to transmit trace data, then program flow and data access operations can be recorded, but high bandwidth requirements are intensified in multi-core systems
Solution Approach 1:
The patent extracts only the essential trace information (memory access operations and program flow data) from the full processor activity and transmits only this filtered data through the trace interface. By taking out only the necessary information rather than transmitting all processor signals, the bandwidth requirement is significantly reduced while maintaining the ability to record program flow and data access operations.
Solution Approach 2:
The patent implements partial action by selectively tracing only memory access operations and program flow information rather than capturing all processor activities. The trace interface filters and records only the relevant subset of data needed for debugging and analysis, reducing the overall data volume that needs to be transmitted while still providing sufficient information for system characterization.
3Loss of information
If all memory access operations are recorded using external adapters, then complete program flow and data access information can be obtained, but physical access to the memory interface is required
Solution Approach 1:
The patent implements self-service by incorporating the tracing functionality directly within the processor system through the trace interface. The processor itself generates and makes available the trace data through its internal trace port, eliminating the need for external adapters to physically tap into memory interfaces. The system serves its own tracing needs internally, making complete information available without requiring external physical access.
Data Source
AI summary
A method includes incrementing a counter with transmission of a process data from a first processor to a second processor, periodically decrementing the counter, if the counter is greater than a predetermined floor threshold value, wherein a period is a predetermined time interval; and stalling the first processor, if the counter is above a configurable load threshold value, so as to re-schedule the transmission of the process data from the first processor to the second processor.