Trace Unit with Decoder and Multi-Block Cache for x86 Compatibility
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Solution Overview
Problem
Current processor sequencing techniques do not meet the demands for improved performance and reduced power consumption, especially in portable devices, while maintaining backward compatibility with x86 instruction code.
Innovation Solution
An improved trace unit is introduced, which includes a cache circuit to store and optimize sequences of operations, allowing for efficient sequencing and execution by an execution unit, while maintaining backward compatibility through the use of a decoder circuit, basic block builder circuit, and multi-block builder circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If current sequencing techniques are used, then processor performance is maintained, but power consumption is high and performance improvement does not meet demands
Solution Approach 1:
The patent applies preliminary action by pre-decoding sequences of x86 instructions into sequences of operations and storing them in the cache circuit before execution. This allows the execution unit to retrieve pre-prepared operation sequences rather than decoding instructions in real-time, reducing power consumption while improving performance throughput.
Solution Approach 2:
The patent uses copying by creating and storing copies of decoded operation sequences in the cache circuit. Instead of repeatedly decoding the same x86 instruction sequences, the processor stores copied versions of the decoded operations, enabling fast retrieval and execution with reduced power usage.
2Productivity
If sequences of operations are cached for efficient execution, then performance improves, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the trace unit into distinct functional components: a decoder circuit for decoding x86 instructions, a cache circuit for storing sequences of operations, and an execution unit for executing the sequences. This modular segmentation manages complexity by organizing functions into separate, manageable units.
Solution Approach 2:
The patent uses an intermediary approach by introducing the cache circuit as a mediator between the decoder and execution unit. The cache circuit stores pre-decoded sequences of operations, acting as an intermediary buffer that eliminates the need for complex real-time decoding during execution, thereby improving throughput while managing complexity.
3Adaptability or versatility
If x86 instruction code is maintained for backward compatibility, then code compatibility is preserved, but performance optimization opportunities are limited
Solution Approach 1:
The patent uses copying to maintain backward compatibility while enabling performance optimization. It copies and decodes x86 instruction sequences into internal operation representations, allowing the processor to execute optimized versions of x86 code through the cached operation sequences rather than directly executing original x86 instructions.
Solution Approach 2:
The patent introduces an intermediary translation layer that converts x86 instruction code into sequences of operations. This intermediary representation allows the processor to maintain compatibility with x86 code while optimizing execution through the cache circuit, bridging the gap between compatibility requirements and performance goals.
Data Source
AI summary
An instruction processing circuit for a processor, where the instruction processing circuit is adapted to provide one or more sequence of operations, based on one or more sequence of instructions, to an execution circuit of the processor. The instruction processing circuit includes a cache circuit operable to store a second type of sequence of operations that represents at least a portion of a first type of sequence of operations, where the sequence of operations of the second type includes at most one control transfer that, when present, ends a first portion of a sequence of instructions, where the cache circuit is further configured to store a third type of sequence of operations that represents a set of at least two sequences of operations.