Track and Hold Circuit Active Charge Cancellation
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Solution Overview
Problem
High-speed analog-to-digital converters (ADCs) face linearity issues due to non-linear charge injection by the sampling switch in track and hold circuits, which degrades the conversion accuracy and bandwidth.
Innovation Solution
The implementation of active cancellation circuitry that injects a complementary charge to cancel the non-linear charge injected by the sampling switch, using a dummy switch that is half the size of the sampling switch, and toggling its body to an opposite state to mitigate the effects of drain-body capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a sampling switch is used in track and hold circuit, then the circuit can switch between track and hold modes, but non-linear charge injection degrades linearity and conversion accuracy
Solution Approach 1:
The cancellation transistor is configured to preemptively inject an equal and opposite charge onto the sampling capacitor before the non-linear charge from the sampling switch degrades the signal. This preliminary counter-action neutralizes the harmful charge injection effect, maintaining linearity and conversion accuracy while preserving the switching operation capability
2Speed
If sampling switch size is increased to improve bandwidth, then higher frequency operation is enabled, but non-linear charge injection increases and linearity deteriorates
Solution Approach 1:
The cancellation transistor provides a preemptive counter-charge that neutralizes the non-linear charge injection from the sampling switch. This allows the sampling switch to be sized for optimal bandwidth performance without compromising linearity, as the harmful effects are cancelled in advance
3Measurement precision
If active cancellation circuitry is added, then linearity and spurious-free dynamic range improve, but device complexity increases
Solution Approach 1:
The cancellation transistor is designed as a simplified copy or replica of the sampling switch structure, using the same transistor type and configuration but with inverted control signals. This copying approach achieves effective charge cancellation while maintaining circuit simplicity and avoiding the need for complex cancellation circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the linearity of high-speed ADCs by providing over 90 dB of spurious-free dynamic range at frequencies exceeding 2.5 GHz and reduces third harmonics by 34 dB at 175 MHz and 22 dB at 2.5 GHz, improving overall conversion performance.
Implementation Method 1
The cancellation transistor is configured to inject a charge onto the primary sampling capacitor that cancels a charge injected onto the primary sampling capacitor by the primary switching transistor
Data Source
AI summary
A track and hold circuit includes a primary sampling capacitor, a primary switching transistor, and a cancellation transistor. The primary switching transistor is configured to provide a track state that connects an input signal to the primary sampling capacitor and a hold state that isolates the input signal from the primary sampling capacitor. The cancellation transistor is coupled to the primary sampling capacitor. The cancellation transistor is configured to inject a charge onto the primary sampling capacitor that cancels a charge injected onto the primary sampling capacitor by the primary switching transistor while the primary switching transistor is in the hold state.