Track-and-Hold Receiver Circuit for Sampling Clock Disturbance Cancellation
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Solution Overview
Problem
Conventional high-speed transmission interfaces suffer from performance degradation due to disturbances caused by the sampling clock of the sampling switch through parasitic capacitors, affecting the output of the continuous time linear equalizer (CTLE) or variable gain amplifier (VGA).
Innovation Solution
The receiving module incorporates a track-and-hold circuit with switches and capacitors that utilize inverted clocks to sample and hold input signals, effectively canceling disturbances from the sampling clock, thereby enhancing the overall performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a sampling switch is used to sample the signal, then the sampling operation can be performed, but the parasitic capacitor of the sampling switch causes disturbance to the output of the preceding stage
Solution Approach 1:
The patent utilizes the parasitic capacitors inherent in the sampling switches by connecting them to separate capacitive loads that are not part of the signal path. This converts the harmful parasitic effect into a beneficial feature where the parasitic capacitors perform their capacitive function without disturbing the signal, effectively eliminating the disturbance while maintaining the sampling operation.
2Loss of time
If the sampling clock is used to control the sampling switch, then the sampling timing can be achieved, but the sampling clock causes disturbance through the parasitic capacitor
Solution Approach 1:
The patent extracts the problematic interaction between the sampling clock and the signal path by connecting the parasitic capacitors to separate capacitive loads. This separation removes the harmful coupling effect while preserving the timing function of the sampling clock, allowing the clock to control the sampling switch without causing disturbance to the signal.
3Device complexity
If conventional sampling switch design is used, then the circuit structure is simple, but the overall performance of the IC is affected
Solution Approach 1:
The patent segments the capacitive loading function from the signal path by providing separate capacitive loads for the parasitic capacitors of the sampling switches. This segmentation allows the sampling switch to maintain its simple structure while the separate capacitive loads absorb the parasitic effects, thereby improving overall performance without significantly increasing circuit complexity.
Data Source
AI summary
A receiving module of a transmission interface includes an analog front-end (AFE) circuit and a track-and-hold circuit. The AFE circuit receives an input signal to generate a first intermediate signal. The track-and-hold circuit samples the first intermediate signal according to a first clock to generate a second intermediate signal, and comprises at least one first switch, at least one second switch, at least one first capacitor, and at least one second capacitor. The first and second switches are turned on or off according to the first clock. The first capacitor has first and second terminals. The first terminal is coupled to the AFE circuit. The second terminal receives a second clock. The second capacitor has third and fourth terminals. The third terminal is coupled to the AFE circuit. The fourth terminal receives the second clock. The first clock and the second clock are inverted signals of each other.