Track-and-Hold Circuit Using Duty-Ratio Clock Multiplication
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Solution Overview
Problem
Current track-and-hold circuits are limited to sampling frequencies twice that of the clock frequency, necessitating higher clock frequencies which increase power consumption and reduce timing margins, making it difficult to handle high data rates in communication and measurement applications.
Innovation Solution
The implementation of 2N bias adjusting circuits and 2N sampling circuits that adjust differential clock signals to achieve a duty ratio of (2N-2k+1):(2k-1), allowing the track-and-hold circuit to sample at frequencies four times that of the clock frequency, using differential or single-phase clock signals with adjusted DC bias voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock frequency is increased to achieve higher sampling frequency, then the sampling frequency is improved, but power consumption increases and timing margin decreases
Solution Approach 1:
The patent divides the sampling function into multiple parallel sampling circuits (2N circuits) that operate with different duty ratios of the same clock signal. Instead of increasing clock frequency to achieve higher sampling rate, the system segments the sampling task across multiple circuits that can sample at different phases, effectively multiplying the sampling frequency by 4 or more times the clock frequency without increasing power consumption proportionally.
Solution Approach 2:
The patent changes the duty ratio parameter of the clock signal to achieve different sampling frequencies. By adjusting the duty ratio of the same clock signal across different sampling circuits, the system can achieve 4x or more sampling frequency multiplication without changing the clock frequency itself, thereby avoiding increased power consumption and timing margin reduction.
2Speed
If the clock frequency is increased to handle high data rates, then the data rate handling capability is improved, but timing margin decreases
Solution Approach 1:
The patent segments the high-speed sampling task across multiple parallel sampling circuits operating with different duty ratios. This allows the system to achieve high data rate handling capability through parallel processing rather than increasing clock frequency, thereby preserving timing margins in each individual circuit.
Solution Approach 2:
The patent introduces a new dimension of duty ratio variation across multiple sampling circuits. Instead of solving the high data rate problem by increasing frequency in one dimension, the system uses multiple circuits with different duty ratios, effectively adding a dimensional approach that achieves high data rate handling while maintaining adequate timing margins.
3Productivity
If the clock frequency is increased to achieve higher sampling frequency, then the sampling frequency is improved, but circuit design complexity increases
Solution Approach 1:
The patent makes a single clock signal serve multiple functions by distributing it to 2N sampling circuits with different duty ratios. The same clock signal achieves multiple sampling frequencies simultaneously across different circuits, eliminating the need for multiple clock generating circuits and reducing overall system complexity despite achieving high sampling frequencies.
Solution Approach 2:
The patent achieves different sampling frequencies by changing only the duty ratio parameter of the clock signal across different sampling circuits, rather than requiring different clock frequencies. This parameter-based differentiation simplifies the circuit design by using a universal clock source with variable duty ratios instead of multiple independent clock generating circuits.
Data Source
AI summary
Bias adjusting circuits (1_(2k-1), 1_2k) (where k is an integer equal to or greater than 1 and equal to or less than N, and N is an integer equal to or more than 2) adjust DC bias voltage of at least one of clock signals such that a duty ratio, which is a ratio between a period in which a clock signal is High as to a clock signal and a period in which the clock signal is Low thereasto, becomes (2N−2k+1):(2k−1). Sampling circuits switch between a track mode in which an output signal tracks an input signal, and a hold mode in which a value of the input signal at a timing of switching from the track mode to the hold mode is held and output, in accordance with clock signals output from the bias adjusting circuits (2_1 to 2_2N).